Skyworks Solutions, Inc. [978] 241-7000
Fax [978] 241-7906
Email sales@skyworksinc.com
www.skyworksinc.com
1
Specifications subject to change without notice. 3/99A
GaAs IC Linear Power Amplifier
Features
IS-136/54 TDMA
IS-95 CDMA
Linear Power up to 28 dBm Nominal
Nominal 6 V Operation, Single Supply
Operation
Efficiency Greater Than 35%
High Power SSOP-28 Batwing Package
with Slug
SSOP-28 Slug
AP105-69
Description
The AP105-69 is a low cost IC power amplifier designed
for the 824849 MHz frequency band. It features 5 cell
battery operation and operates from 5 V to 7.5 V with
excellent linearity, and high efficiency. An integrated
DC/DC converter supplies -4 V to the power amplifier and
can supply 1.5 mA to an external circuit. The amplifier is
designed to be stable over a temperature range of -30 to
100C and over 3:1 VSWR loads.
Characteristic
Condition
Frequency
Min.
Typ.
Max.
Unit
Digital Mode
P
OUT
(Reference at Output Pin Leads)
0<P
IN
<5
824849 MHz
28
dBm
Efficiency
P
OUT
= 28 dBm
37
%
Large Signal Gain
P
IN
= -20 dBm
26
dB
Idle Current
P
IN
= -60 dBm
150
200
mA
Noise in the Receive Band
P
OUT
= 28 dBm
-100
-95
dBm
R
X
Band = 869894 MHz
R
X
Bandwidth = 30 kHz
Reference Current
P
OUT
= 28 dBm
1
5
mA
Input VSWR
P
IN
= -30 to +7 dBm
2.5:1
Analog Mode
P
OUT
0<P
IN
<5
824849 MHz
28
dBm
Efficiency
P
OUT
= 28 dBm
40
%
Large Signal Gain
P
IN
= -20 dBm
24
dB
Idle Current
P
IN
= -60 dBm
50
90
mA
Electrical Specifications at 25C
0.394 (10.00 mm)
0.386 (9.80 mm)
R 0.010
(0.25 mm) MAX.
0.157 (3.99 mm)
0.150 (3.81 mm)
0.244
(6.20 mm)
0.228
(5.79 mm)
0.087 (2.21 mm)
0.083 (2.11 mm)
0.120
(3.05 mm)
MAX.
28
15
14
0.025 BSC
0.060 (1.52 mm) REF.
0.145 (3.68 mm) REF.
0.063 (1.60 mm)
0.049 (1.24 mm)
0.050 (1.27 mm)
0.016 (0.41 mm)
0.004 MAX.
(0.010 mm)
R 0.33 (0.013 mm)
0.020 (0.008 mm)
0.38 (0.015 mm)
MAX. X 45
CHAMFER
PIN 1
INDICATOR
2
Skyworks Solutions, Inc. [978] 241-7000
Fax [978] 241-7906
Email sales@skyworksinc.com
www.skyworksinc.com
Specifications subject to change without notice. 3/99A
GaAs IC Linear Power Amplifier
AP105-69
Input Power (dBm)
P
OUT
, P.A.E. vs. P
IN
Output Power (dBm)
Power Added Efficiency (%)
25
20
15
10
30
50
40
30
20
10
0
60
-6
-4
-2
0
2
4
5
0
6
8
Input Power (dBm)
Distortion. vs. P
IN
IM3, IM5, IM7 (dBc)
-6
-4
-2
0
2
4
6
8
80
70
60
50
40
30
20
10
0
IM7
IM5
IM3
Input Power (dBm)
P
OUT
, Gain vs. P
IN
30
25
30
25
20
15
10
20
15
10
5
0
35
-6
-4
-2
0
2
4
6
8
Output Power (dBm)
Gain (dB)
Output Power (dBm)
Bias Current vs. P
OUT
Bias Current (mA)
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
17 18 19 20 21 22 23 24 25 26 27 28
Typical Performance Data (824849 MHz)
Characteristic
Condition
Frequency
Min.
Typ.
Max.
Unit
Voltage
5
6
7.5
V
IM3@ Rated P
OUT
P
OUT
= 31 dBm PEP
-24
dBc
IM5@ Rated P
OUT
P
OUT
= 31 dBm PEP
-34
dBc
IM7@ Rated P
OUT
P
OUT
= 31 dBm PEP
-38
dBc
Harmonic Power
2fo
-30
dBc
3fo
-45
Modulation
Channel Spacing = 30 kHz,
832 Channels, Pi/4 QPSK
P
ADJ
30 kHz
-28
dBc
60 kHz
-49
90 kHz
-60
Input Impedance
50
Operating Characteristics at 25C
Skyworks Solutions, Inc. [978] 241-7000
Fax [978] 241-7906
Email sales@skyworksinc.com
www.skyworksinc.com
3
Specifications subject to change without notice. 3/99A
GaAs IC Linear Power Amplifier
AP105-69
Standby Mode
The power amplifier should be turned off whenever
possible in order to reduce the overall power consumption.
The AP105 can be turned off in several ways. The simplest
is to switch the bias controller supply voltage (Pin 1) open.
This, in effect, switches the gate voltages to V
SS
. The bias
current of the PA in this condition will drop to less than
1 mA. By adding PMOS switches to the drain lines bias-
off currents on the order of a few A can be achieved.
Power Amplifier Typical Configuration
Pin Out Assignments
+4.8
R_Analog
R_Analog
2k
750
1
1
2
2
U2
U1
C1
1 nF
L1
5.6 nH
+5.8
1 n
C3
33 pF
C2
33 pF
C4
R2
18k
RF_INPUT
V
REF
V
GS2
V
DS1
V
GS1
RF In
V
DD
V
SS IN
RF Out/V
DS2
RF Out/V
DS2
RF Out/V
DS2
GND
GND
GND
CA
CB
V
SS OUT
V
GEN
GND
GND
GND
GND
GND
AP105
L3
1.5 n
C12
100 p
L2
6.8 n
C11
5.6 p
33 pF
C9
1 n
C10
+5.8
C8
3.3 p
100 n
C5
100 n
C7
100 n
C6
-4 V_EXT
RF_OUTPUT
Output Matching Circuit
The output match for the AP105 is provided externally in
order to improve performance, reduce cost, and add
flexibility. By making use of ceramic surface mount
components with better Qs than GaAs matching
elements, a lower loss matching network can be made.
This lower loss results in higher power and efficiency for
the amplifier. Also, by keeping these elements external the
GaAs die size is reduced and the overall cost is less. This
approach also permits the flexibility to tweak the amplifier
for optimum performance at different powers, and/or
frequencies.
The board schematic demonstrates one way to present
the optimum load match while providing a path for the
DC bias.
Bias Controller Circuit
An on-chip bias controller circuit eliminates the need to
individually adjust the gate bias voltages. This circuit uses
+4.8 V and the negative voltage from the DC converter
(-3.5 V to -4.5 V) to set the gate voltages on each stage
for the proper bias current. Pin 1 can be used to adjust the
bias current between a linear and a saturated mode of
operation. By switching resistors between this pin and
+4.8 V, different quiescent currents can be selected. A
current of 100-200 mA for good linearity in the digital
mode, and a lower current, less than 100 mA, for better
power consumption in the analog mode is optimum.
28
27
26
25
24
19
18
17
16
15
1
2
3
4
5
1
01
1
1
21
31
4
DC/DC
Converter
Bias
Control
Pin 1: V
REF
Sets the quiescent bias current. Nominally +3.5 V for a bias
of 120-200 mA with best gain and linearity. Lower voltages
in the range of +1 to +3.5 V will set the amplifier for less
quiescent bias current. This is useful for analog or
saturated operation where linearity is not critical. A resistor
GaAs IC Linear Power Amplifier
AP105-69
4
Skyworks Solutions, Inc. [978] 241-7000
Fax [978] 241-7906
Email sales@skyworksinc.com
www.skyworksinc.com
Specifications subject to change without notice. 3/99A
GaAs IC Linear Power Amplifier
AP105-69
divider network can be used with the +4.8 V regulated
supply to achieve the nominal voltage. The input
impedance of this pin is 2 k
. A switch can be used to
change the resistance and toggle the amp between digital
and analog mode.
Pin 2: V
GS2
Second stage gate voltage tap. Should be bypassed with
a 1nF capacitor. This value is not critical.
Pin 3: V
DS1
First stage drain bias feed. Requires a matching inductor
with good RF bypassing and the +5.8 V nominal supply
voltage.
Pin 4: V
GS1
First stage gate voltage. Requires RF bypassing and an
18K resistor to properly bias the first stage.
Pin 5: RF In
50
RF input.
Pin 6-14: GND
Connect to ground.
Pin 15: V
GEN
Supply voltage to DC/DC converter. Requires +4.8 V with
a 100 nF bypassing capacitor.
Pin 16: V
SS OUT
Negative output voltage from the DC/DC converter. A
100 nF capacitor is required. This voltage should be
supplied to the bias controller network at Pin 27. External
circuitry (LCD display, driver amplifiers, etc.) can tap off
the negative voltage at this point. Maximum current 2 mA.
Pin 17: CB
Switched capacitor for DC/DC converter. 100 nF capacitor
should be connected between Pin 17 and Pin 18 with
minimal distance between the capacitor and the chip.
Pin 18: CA
Switch capacitor for DC/DC converter, shared with Pin 17.
Pin 19-23: GND
Connect to ground.
Pin 24-26: RF Out/V
DS2
RF output and bias feed for the second stage drain. Output
matching circuitry is required to transform the optimum
load impedance to 50
. The circuit must also provide a
path for the +5.8 V nominal DC bias and have good
RF bypassing.
Pin 27: V
SS IN
Negative voltage for the bias controller circuit. The negative
voltage from the DC/DC converter (Pin 16) should be fed
to this pin.
Terminal
Symbol
Function
1
V
REF
Reference Voltage
2
V
GS2
Gate Voltage 2
3
V
DS1
Supply Voltage 1
4
V
GS1
Gate Voltage 1
5
RF In
RF Input
6
GND
Ground
7
GND
Ground
8
GND
Ground
9
GND
Ground
10
GND
Ground
11
GND
Ground
12
GND
Ground
13
GND
Ground
14
V
NGND
Voltage Generator Ground
15
V
GEN
Generator Voltage
16
V
SS OUT
Bias Voltage Out
17
CB
Generator Flying Cap
18
CA
Generator Flying Cap
19
GND
Ground
20
GND
Ground
21
GND
Ground
22
GND
Ground
23
GND
Ground
24
RF Out/V
DS2
RF Output/Supply Voltage 2
25
RF Out/V
DS2
RF Output/Supply Voltage 2
26
RF Out/V
DS2
RF Output/Supply Voltage 2
27
V
SS IN
Negative Bias Voltage Input
28
V
DD
Positive Bias Voltage Input
Pin Configuration
Pin 28: V
DD
Bias controller supply voltage. The regulated 4.8 V supply
must be connected to this pin. Disconnecting this voltage
will turn the PA bias off. A switch at this pin can turn the
PA on or off while leaving V
GEN
connected and the
negative supply unchanged.
Characteristic
Value
Drain Voltage (V
DD
)
10 V
Bias Voltage (V
SS
)
-6 V
Reference Voltage (V
REF
)
6 V
Power Input (P
IN
)
12 dBm
Operating Temperature (T
OPT
)
-30 to +100C
Storage Temperature (T
STG
)
-35 to +120C
Absolute Maximum Ratings
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