CXA2094Q

48 pin QFP (Plastic)

E97725A86

US Audio Multiplexing Decoder

Description

The CXA2094Q is an IC designed as a decoder for

the Zenith TV Multi-channel System and also
corresponds with I

C BUS. Functions include stereo

demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction. Various kinds of
filters are built in while adjustment and mode control
are all executed through I

C BUS.

Features
· Adjustment free of VCO and filter.
· Audio multiplexing decoder and dbx noise

reduction decoder are all included in a single chip.
Almost any sort of signal processing is possible
through this IC.

· All adjustments are possible through I

C BUS to

allow for automatic adjustment.

· Various built-in filter circuits greatly reduce external

parts.

· There are two systems for external inputs.
· There is an additional SAP output.

Absolute Maximum Ratings (Ta = 25°C)
· Supply voltage

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

0.6

Range of Operating Supply Voltage

9 ± 0.5

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

A license of the dbx-TV noise reduction system is

required for the use of this device.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

9 10 11 12

36 35 34

SDA

SCL

DGND

MANIN

COMPIN

PCINT2

PCINT1

VCATC

VCAIN

VEOUT

VETC

VEWGT

SAPIN

SAPOUT

TVOUT-L

TVOUT-R

AUX2-L

TVOUT-S

AUX2-R

AUX1-L

AUX1-R

ESAPIN

SOUT

VCAWGT

VGR

GND

SAPTC

SUBOUT

STIN

MAINOUT

PLINT

IREF

NOISETC

Standard I/O Level
· Input level

COMPIN (Pin 12)

100mVrms
245mVrms (Selected by INSW)

AUX1-L/R (Pins 42 and 41)

490mVrms

AUX2-L/R (Pins 45 and 44)

490mVrms

· Output level

TVOUT-L/R (Pins 47 and 46)

490mVrms

Pin Configuration (Top View)

CXA2094Q

Block Diagram

AIN

PLI

I
N

I
S

-
L

I
R

I
C

/
2

/
4

I
S

I
N

"
P

I
N

"
S

"
N

I
S

/
F

/
S

I
D

"
S

(
+

)

I
/
F

(
+

)

X1-

-
R

-
L

-
R

/
I
N

I
X

-
S

I
N

CXA2094Q

Pin Description

(Ta = 25°C, V

= 9V)

7.5k

35µ

2.1V

10.5k

147

10k

53k

No.

Symbol

Pin
voltage

Equivalent circuit

Description

SCL

DGND

MAININ

4.0V

Serial clock input pin.
V

> 3.0V

< 1.5V

Digital block GND.

Input the (L + R) signal from
MAINOUT (Pin 4).

MAINOUT

4.0V

(L + R) signal output pin.

147

15k

200µ

CXA2094Q

Pin
No.

Symbol

Pin
voltage

Equivalent circuit

Description

PCINT1

PCINT2

PLINT

4.0V

5.1V

Stereo block PLL loop filter
integrating pin.

Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)

147

20k

26µ

20k

10k

20k

50µ

20k

22k

30k

147

10k

147

COMPIN

4.0V

Audio multiplexing signal
input pin.

24k

34k

14k

147

24k

CXA2094Q

No.

Symbol

Pin
voltage

Equivalent circuit

Description

VGR

IREF

GND

1.3V

Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)

Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based
on the current which flows to
this pin.
(Connect a 62k

(±1%)

resistor between this pin and
GND.)

Analog block GND.

Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)

SAPTC

4.5V

10k

50µ

40k

30k

30p 1.8k

16k

6.3k

147

30k

15k

30k

11k

9.7k

19.4k

2.06k

147

11k

Supply voltage pin.

CXA2094Q

No.

Symbol

Pin
voltage

Equivalent circuit

Description

SUBOUT

STIN

NOISETC

4.0V

3.0V

(L-R) signal output pin.

Input the (L-R) signal from
SUBOUT (Pin 22).

Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)

SAPIN

4.0V

Input the (SAP) signal from
SAPOUT (Pin 25).

147

580

14.4k

580

10P

Vcc

23k

147

18k

20k

11.7k

23k

147

18k

3.3k

Vcc

10k

Vcc

200k

SAPOUT

4.0V

SAP FM detector output pin.

24k

10µ

580

Vcc

580

50µ

10k

147

CXA2094Q

No.

Symbol

Pin
voltage

Equivalent circuit

Description

VETC

4.0V

1.7V

Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3k

resistor in series

between this pin and GND.)

Determine the restoration
time constant of the variable
de-emphasis control effective
value detection circuit.
(The specified restoration
time constant can be obtained
by connecting a 3.3µF
capacitor between this pin
and GND.)

VEWGT

4.0V

Weight the variable
de-emphasis control effective
value detection circuit.
(Connect a 0.047µF capacitor
and a 3k

resistor in series

between this pin and GND.)

Vcc

36k

2.9V

580

147

580

30k

8µ

50µ

20k

7.5µ

50µ

Vcc

7.5k

147

CXA2094Q

No.

Symbol

Pin
voltage

Equivalent circuit

Description

VEOUT

VCAIN

VCAWGT

4.0V

Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 34
and 35.)

VCA input pin.
Input the variable
de-emphasis output signal
from Pin 34 via a coupling
capacitor.

Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9k

resistor in series

between this pin and GND.)

VCATC

1.7V

Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(The specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)

Vcc

10k

580

30k

36k

2.9V

580

580 147

40k

50µ

8µ

50µ

20k

7.5µ

20k

47k

CXA2094Q

No.

Symbol

Pin
voltage

Equivalent circuit

Description

ESAPIN

4.0V

Additional SAP output pin.

Input the signal from SOUT
(Pin 38).

SOUT

4.0V

15k

200µ

147

47k

10k

AUX1-R

4.0V

Right channel external input
1 pin.

AUX1-L

4.0V

Left channel external input
1 pin.

AUX2-R

4.0V

Right channel external input
2 pin.

AUX2-L

4.0V

Left channel external input
2 pin.

27.5k

47k

10k

TVOUT-S

4.0V

Optional output pin.
From this pin monaural or
additional SAP is output.

TVOUT-R

4.0V

TVOUT right channel output
pin.

TVOUT-L

4.0V

TVOUT left channel output
pin.

580

CXA2094Q

Electrical Characteristics

COMPIN input level

(100% modulation level)

(Ta = 25

°
C, V

= 9V)

Item

Current consumption

Main output level

Main de-emphasis

frequency characteristic

Main LPF frequency

characteristic

Main distortion

Main overload distortion

Main S/N

Sub output level

Sub LPF frequency

characteristic

Sub distortion

Sub overload distortion

Sub S/N

SAP

Crosstalk

No.

Signal

Icc

Vmain

FCdeem

FCmain

THDm

THDmmax

SNmain

Vsub

FCsub

THDsub

THDsmax

SNsub

CTst

Mode

MONO

SAP

Input pin

Min.

440

1.2

3.0

150

3.0

Typ.

490

1.0

0.1

0.15

190

0.5

0.1

0.2

Max.

540

1.0

0.5

230

1.0

2.0

Unit

mVrms

Input signal

No signal

Mono 1kHz 100% mod.

Pre-em. ON

Mono 5kHz 30% mod.

Pre-em. ON

Mono 12kHz 30% mod.

Pre-em. ON

Mono 1kHz 100% mod.

Pre-em. ON

Mono 1kHz 200% mod.

Pre-em. OFF

Mono 1kHz,

Pre-em. ON

SUB (L-R) 1kHz,

100% mod., NR OFF

SUB (L-R) 12kHz,

30% mod., NR OFF

SUB (L-R) 1kHz,

100% mod., NR OFF

SUB (L-R) 1kHz,

200% mod., NR OFF

SUB (L-R) 1kHz,

NR OFF

SUB (L-R) 1kHz,

100% mod., NR ON,

SAP Carrier (5f

)

Measurement

conditions

20 log

('5k'/ '1k')

20 log

('12k'/ '1k')

20 log

('100%'/ '0%')

20 log

('12k'/ '1k')

20 log

('100%'/ '0%')

20 log

('NRSW = 0'/

'NRSW = 1')

Filter

15kLPF

1kBPF

Output

46/47

= 15.734kHz

Main (L + R)

(Pre-Emphasis : OFF)

SUB (L R) (dbx-TV : OFF)

Pilot

SAP Carrier

INSW = 0

= 245mVrms

= 490mVrms

= 49mVrms

= 147mVrms

INSW = 1

= 100mVrms

= 200mVrms

= 20mVrms

= 60mVrms

CXA2094Q

No.

Item

Sub pilot leak

Stereo ON level

Stereo ON/OFF

hysteresis

SAP output level

SAP LPF frequency

characteristic

SAP distortion

SAP S/N

SAP

Cross talk

SAP ON level

SAP ON/OFF hysteresis

ST separation 1 L

ST separation 1 R

ST separation 2 L

ST separation 2 R

TVOUT output level

TVOUT cross talk

TVOUT

muted amount

Symbol

PCsub

THst

HYst

Vsap

FCsap

THDsap

SNsap

CTsap

THsap

HYsap

STLsep1

STRsep1

STLsep2

STRsep2

Vtv

CTtv1

CTtv2

MUtv1

MUtv2

Mode

SAP

EXT

INT

EXT

INT

EXT

Input pin

41/42

44/45

41/42

44/45

41/42

44/45

Min.

9.0

2.0

150

3.0

12.0

2.0

0.5

Typ.

6.0

190

2.5

9.0

4.0

Max.

3.0

10.0

230

2.5

6.0

6.5

6.0

0.5

Unit

mVrms

Input signal

PILOT (f

) 0dB

Change

PILOT (f

) Level

SAP 1kHz 100% mod.

NR OFF

SAP 10kHz 30% mod

NR OFF

SAP 1kHz 100% mod

NR OFF

SAP 1kHz, NR OFF

SAP 1kHz 100% mod.

NR ON, Pilot (f

)

Change

SAP Carrier (5f

)

Level

ST-L 300Hz 30% mod

NR ON

ST-R 300Hz 30% mod

NR ON

ST-L 3kHz 30% mod

NR ON

ST-R 3kHz 30% mod

NR ON

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

MONO 1kHz 100% mod.

Pre-em. ON

MONO 1kHz 100% mod.

Pre-em. ON

Sine wave 1kHz,

490mVrms

Measurement

conditions

0dB = 49mVrms

20 log (`on

level'/ 'off level')

20 log

('10k'/ '1k')

20 log

('100%'/ '0%')

20 log ('NRSW

= 1'/ 'NRSW = 0')

0dB = 147mVrms

20 log (`on

level'/'off level')

0dB = 490mVrm

0dB = 490mVrms

EXT

INT

0dB = 490mVrms

INT

EXT

20 log

(M1 =

"0"/M1 = "1")

20 log

(M1 =

"0"/M1 = "1")

Filter

BPF

15kLPF

1kBPF

15kLPF

1kBPF

Output

BUS

RETURN

BUS

RETURN

46/47

CXA2094Q

No.

Item

TVOUT DC offset

TVOUT distortion

TVOUT S/N

TVOUT overload distortion

Symbol

OStv

THDtv

SNtv

THDtvmax

Mode

INT

EXT

Input pin

41/42

44/45

41/42

44/45

41/42

44/45

Min.

Typ.

0.01

0.1

Max.

0.5

1.0

Unit

Input signal

No signal

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

2Vrms

Measurement

conditions

Mute (M1 = 0)/

DC difference

when there is

no signal

20 log

('490mVrms'/

'No signal')

Filter

15kLPF

Output

46/47

CXA2094Q

Electrical Characteristics Measurement Circuit

.
7

AIN

I
N

I
R

I
S

-
L

-
R

-
L

-
S

-
R

-
L

-
R

I
N

.
7

.
3

.
0

I
L

I
G

.
7

I
G

.
0

.
7

.
9

.
7

SIG

I
G

CXA2094Q

Adjustment Method (Input signal level is the case when standard input signal is 245mVrms)

1. ATT adjustment

1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then,

adjust the "ATT" data for ATT adjustment so that the TVOUT-L output goes to the standard value

(490mVrms).

3) Adjustment range: ±30%

Adjustment bits:

4 bits

2. Separation adjustment

1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz

NR-ON) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce TVOUT-R output

to the minimum.

3) Next, set the frequency only of the input signal to 3kHz and adjust the "SPECTRAL" adjustment data to

reduce TVOUT-R output to the minimum.

4) The adjustments in 2 and 3 above are performed to optimize the separation.

5) "WIDEBAND"

"SPECTRAL"

Adjustment range: ±30%

Adjustment range: ±15%

Adjustment bits:

6 bits

Adjustment bits:

6 bits

Adjust this through Tuner and IF when this IC is mounted on the set.

CXA2094Q

Description of Operation

The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.

Fig. 1. Base band spectrum

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

Fig 3. dbx-TV block

PEAK DEV

kHz

L + R

50 15kHz

L-R

dbx-TV

AM-DSB-SC

SAP

dbx-TV NR

FM 10kHz

50 10kHz

TELEMETRY

FM 3kHz

= 15.734kHz

6.5f

I
L

(COMPIN)

STEREO LPF

PLL

(VCO 8f

)

0°

90°

0°

MODE
CONTROL

PILOT

DET

MVCA

PILOT

CANCEL

MAIN LPF DE.EM

(MAIN OUT)

L + R

4.7µ

(MAIN IN)

L-R (DSB)

DET

INJ.

LOCK

SUBVCA

SUB LPF

WIDEBAND

(SUBOUT) (ST IN)

4.7µ

NR SW

dbx-TV

BLOCK

MATRIX

(Lch)

(Rch)

MODE

CONTROL

(SAP IN)

4.7µ

SAP(FM)

DET

SAP LPF

I C BUS
DECODER
MODE
CONTROL

SAP BPF

(SAP OUT)

L R

to
TVSW

NOISE

DET

I C BUS
DECODER

SAP
DET

C BUS

DECODER

(TVOUT-S)

LPF

4.7µ

(SOUT)

(ESAPIN)

NR SW

FIXED

DEEMPHASIS

VARIABLE

DEEMPHASIS

(VE OUT) (VCA IN)

to
MATRIX

4.7µ

HPF

LPF

RMS

DET

RMS

DET

VCA

(ST IN)

(SAP IN)

CXA2094Q

Fig. 4. Switch block

(1) L + R (MAIN)

After the audio multiplexing signal input from COMPIN (Pin 12) passes through MVCA, the SAP signal

and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the

L R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened

(de-emphasized) and input to the matrix.

(2) L R (SUB)

The L R signal follows the same course as L + R before the pilot signal is canceled. L R has no

carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM

modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)

to be used for the demodulation of the L R signal. In the last stage, the residual high frequency

components are removed by SUB LPF and the L R signal is input to the dbx-TV block via the NRSW

circuit after passing through SUBVCA.

(3) SAP

SAP is an FM signal using 5f

as a carrier as shown in the Fig. 1. First, the SAP signal only is

extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency

components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal

is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 25 output is

soft muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is

performed by detecting the 5f

carrier amplitude. NOISE discrimination is performed by detecting the

noise near 25kHz after FM detection of SAP signal.

(5) dbx-TV block

Either the L R signal or SAP signal input respectively from ST IN (Pin 23) or SAP IN (Pin 27) is

selected by the mode control and input to the dbx-TV block.

The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de-

emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external

capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a

current to a voltage using an operational amplifier and then input to the matrix.

(Lch) (Rch)

(AUX1-L)

(AUX1-R)

from MATRIX

(TVOUT-L)

(TVOUT-R)

TVSW

(AUX2-L) (AUX2-R)

CXA2094Q

The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of

effective value detection circuits. Each of the effective value detection circuits passes the input signal

through a predetermined filter for weighting before the effective value of the weighted signal is

detected to provide the control signal.

(6) Matrix, TVSW

The signals (L + R, L R, SAP) input to "MATRIX" become the outputs for the ST-L, ST-R, MONO and

SAP signals according to the mode control and whether there is ST / SAP discrimination.

"TVSW" switches the "MATRIX" output signal, external input signal (input to AUX1-L, R (Pins 42 and

41)), external input signal (input to AUX2-L, R (Pins 45 and 44)) and external forced MONO.

(7) Others

"MVCA" is a VCA which adjusts the input signal level to the standard level of this IC.

"Bias" supplies the reference voltage and reference current to the other blocks. The current flowing to

the resistor connecting IREF (Pin 15) with GND become the reference current.

CXA2094Q

SPECTRAL (6)

WIDEBAND (6)

0000

0001

0010

0011

0100

SLAVE RECEIVER

84H (1000 0100)

SLAVE TRANSMITTER

85H (1000 0101)

Register Specifications

Slave address

Register table

Status Registers

DATA

SUB ADDRESS

MSB

LSB

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

TEST-DA

TVSW

INSW

TEST1

EXT

SMD

NRSW

ATTSW

FOMO

FST

SAPC

FEXT1

FEXT2

STA1

BIT7

POWER
ON RESET

STA2

BIT6

STEREO

STA3

BIT5

SAP

STA4

BIT4

NOISE

STA5

BIT3

STA6

BIT2

STA7

BIT1

STA8

BIT0

ATT (4)

: Don't Care

CXA2094Q

Description of Registers

Control registers

ATT

SPECTRAL

WIDEBAND

TEST-DA

TEST1

FST

NRSW

FOMO

TVSW

FEXT1

FEXT2

EXT

SMD

ATTSW

INSW

SAPC

Input level adjustment

Adjustment of stereo separation (3kHz)

Adjustment of stereo separation (300Hz)

Turn to DAC test mode and VCO adjustment mode by means
of TEST-DA = 1.

Turn to test mode by means of TEST = 1.
(Adjustment of FILTER)

Turn to forced stereo by means of FST = 1.

Selection of the output signal (Stereo mode, SAP mode)

Turn to forced MONO by means of FOMO = 1.
(Left channel only is MONO during SAP output.)

Selection of TV mode or external input mode for TVOUT
output

External input 1 forced MONO (1: forced MONO ON)

External input 2 forced MONO (1: forced MONO ON)

Selection of external input 1 mode or external input 2 mode
for TVOUT output. (TVSW = 1)

Selection of TVOUT mute ON/OFF
(0: mute ON, 1: mute OFF)

Selection of L + R or additional SAP

Turn the input stage MVCA off when ATTSW = 1.

Selection of standard input level

Selection of SAP mode or L + R mode according to the
presence of SAP broadcasting

Contents

Number
of bits

Classifi-
cation

Standard
setting

Classification U: User control

A: Adjustment

S: Proper to set

T: Test

Status registers

PONRES

STEREO

SAP

NOISE

POWER ON RESET detection;

1: RESET

Stereo discrimination of the COMPIN input signal;

1: Stereo

SAP discrimination of the COMPIN input signal;

1: SAP

Noise level discrimination of the SAP signal;

1: Noise

Number of bits

Contents

CXA2094Q

Description of Control Registers

ATT (4):

Adjust the signal level input to COMPIN (Pin 12) to the standard input level.

Variable range of the input signal: standard input level 5.0dB to +3.0dB

0 = Level min.

F = Level max.

SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.

0 = Level max.

3F = Level min.

WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment.

0 = Level min.

3F = Level max.

TEST-DA (1): Set DAC output test mode.

0 = Normal mode

1 = DAC output test mode

In addition, the following output are present at Pin 47.

TVOUT-L (Pin 47): DA control DC level

TEST1 (1):

Monitor SAP BPF and NR BPF output.

0 = Normal mode

1 = SAP BPF and NR BPF output

In addition, the following outputs are present at Pins 47 and 46.

TVOUT-L (Pin 47): SAP BPF OUT

TVOUT-R (Pin 46): NR BPF OUT

FST (1):

Select forced STEREO mode

0 = Normal mode

1 = Forced stereo mode

NRSW (1):

Select stereo mode or SAP mode

0 = Stereo mode

1 = SAP mode

CXA2094Q

FOMO (1):

Select forced MONO mode

0 = Normal mode

1 = Forced MONO mode

FEXT1 (1):

Turn external input [1] to forced MONO.

0 = Normal mode

1 = External input [1] is forced MONO.

Input the same signal to both AUX1-L and AUX1-R.

FEXT2 (1):

Turn external input [2] to forced MONO

0 = Normal mode

1 = External input [2] is forced MONO

Input the same signal to both AUX2-L and AUX2-R.

TVSW (1):

Select TV mode or external input mode for TVOUT output.

0 = TV mode

1 = External input mode

EXT (1):

Select external input [1] mode or external input [2] mode for TVOUT output. (TVSW = 1)

0 = External input [1] mode

1 = External input [2] mode

M1 (1):

Mute the TVOUT-L and TVOUT-R output.

0 = Mute ON

1 = Mute OFF

SMD (1):

Select L + R or additional SAP signal

0 = L + R output is selected

1 = additional SAP output is selected

ATTSW (1):

Select BYPASS SW of MVCA

0 = Normal mode

1 = MVCA is passed

INSW (1):

Select standard input level of COMPIN (Pin 12)

0 = 245mVrms

1 = 100mVrms

SAPC (1):

Select the SAP signal output mode

When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC.

0 = L + R output is selected

1 = SAP output is selected

CXA2094Q

Description of Mode Control

Priority ranking: M1 > TVSW/EXT > (NRSW & FOMO & SAPC)

NRSW

FOMO

SAPC

TVSW/EXT

"Select dbx input and TV decoder output"

Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)

· During ST input:

left channel: L,
right channel: R

· During other input: left channel: L + R,

right channel: L + R

NRSW = 1 (SAP output)
· When there is "SAP" during SAP

discrimination
left channel: SAP, right channel: SAP

· When there is "No SAP", output is the

same as when NRSW = 0.

"Select dbx input and TV decoder output"

Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)

As on the left

NRSW = 1 (SAP output)
· Regardless of the presence of SAP

discrimination,
dbx input: "SAP"
left channel: SAP, right channel: SAP

However, when there is no SAP, SAPOUT
output is soft muted (7dB)

Mode control

SAPC = 0

SAPC = 1

"Forced MONO"

FOMO = 1
· During SAP output: left channel: L + R, right channel: SAP
· During ST or MONO output: left channel: L + R, right channel: L + R

Change the selection conditions for "MONO or ST output" and "SAP output".

SAPC = 0: Switch to SAP output when there is SAP discrimination.

Do not switch to SAP output when there is no SAP discrimination.

SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.

"MUTE"

M1 = 0: TVOUT-L, R, S output is muted.

"TV mode/external input mode selection"

TVSW = 0: Set TVOUT-L, R output to TV mode.
TVSW = 1: Set TVOUT-L, R output to external input mode.
EXT = 0:

Set TVOUT-L, R output to external input [1] mode. (TVSW = 1)

EXT = 1:

Set TVOUT-L, R output to external input [2] mode. (TVSW = 1)

CXA2094Q

Decoder Output and Mode Control Table 1 (SAPC = 1)

Note

(SAP) : The SAPOUT output signal is soft muted (approximately 7dB).

The signal is soft muted when NOISE = 1.

: Don't care.

SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is

inputted in the weak electric field.

Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.

"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

MUTE

L + R

SAP

MONO

SAP

L + R

SAP

MUTE

L + R

(SAP)

L + R

(SAP)

L R

MUTE

L + R

L R

STEREO

MUTE

L + R

SAP

L + R

SAP

(SAP)

L + R

(SAP)

MUTE

L + R

MUTE

L + R

MONO & SAP

SAP

L + R

SAP

(SAP)

L + R

(SAP)

L R

MUTE

L + R

STEREO & SAP

SAP

L + R

SAP

(SAP)

L + R

(SAP)

Input signal mode

Mode detection

Mode control

dbx
input

Output

SAP

NOISE

NRSW

FOMO

SAPC

Lch

Rch

CXA2094Q

Decoder Output and Mode Control Table 2 (SAPC = 0)

MUTE

L + R

MUTE

L + R

MONO

MUTE

L + R

(SAP)

L + R

(SAP)

L R

MUTE

L + R

L R

STEREO

MUTE

L + R

L R

MUTE

L + R

(SAP)

L + R

(SAP)

MUTE

L + R

MUTE

L + R

SAP

MONO & SAP

SAP

L + R

SAP

MUTE

L + R

MUTE

L + R

(SAP)

L + R

(SAP)

L R

MUTE

L + R

SAP

STEREO & SAP

SAP

L + R

SAP

L R

MUTE

L + R

(SAP)

L + R

(SAP)

Input signal mode

Mode detection

Mode control

dbx
input

Output

SAP

NOISE

NRSW

FOMO

SAPC

Lch

Rch

Note

(SAP) : The SAPOUT output signal is soft muted (approximately 7dB).

The signal is soft muted when NOISE = 1.

: Don't care.

SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is

inputted in the weak electric field.

Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.

"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

CXA2094Q

Mode Control Table 3

TV (L) / TV (R) are selected in MATRIX

TV (L): MONO, ST-L, SAP, (SAPBPFout, D/Aout)

TV (R): MONO, ST-R, SAP, (NRBPFout, STVCO freerun (4f

))

TVSW

FEXT2

FEXT1

EXT

TVOUT-L

MUTE

TV (L)

AUX1-L

AUX2-L

TVOUT-R

MUTE

TV (R)

AUX1-R

AUX1-L

AUX2-R

AUX2-L

C BUS block items (SDA, SCL)

C BUS load conditions: Pull-up resistor 4k

(Connect to +5V)

Load capacity 200pF (Connect to GND)

High level input voltage

Low level input voltage

High level input current

Low level input current

Low level output voltage SDA (Pin 48) during 3mA inflow

Maximum inflow current

Input capacitance

Maximum clock frequency

Minimum waiting time for data change

Minimum waiting time for start of data transfer

Low level clock pulse width

High level clock pulse width

Minimum waiting time for start preparation

Minimum data hold time

Minimum data preparation time

Rise time

Fall time

Minimum waiting time for stop preparation

SCL

BUF

: STA

LOW

HIGH

: STA

: DAT

: STO

3.0

4.7

4.0

4.7

4.0

4.7

250

4.7

5.0

1.5

0.4

100

300

µA

kHz

µs

No.

Item

Symbol

Min.

Typ.

Max.

Unit

CXA2094Q

SDA

SCL

Start Condition S

Stop Condition P

HIZ

C BUS Signal

There are two I

C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.

· Accordingly there are 3 values outputs, H, L and HIZ.

· I

C transfer begins with Start Condition and ends with Stop Condition.

SDA

SCL

BUF

S t

: STA

LOW

: DAT

HIGH

: STA

: STO

: DAT

C BUS Control Signal

CXA2094Q

· I

C data Write (Write from I

C controller to the IC)

Data can be transferred in 8-bit units to be

set as required.

Sub address is incremented automatically.

· I

C data Read (Read from the IC to I

C controller)

· Read timing

Data Read is performed during SCL rise.

Address

SCL

ACK

DATA

ACK

SDA

H during Read

HIZ

DATA

IC output SDA

SCL

MSB

LSB

ACK

Read timing

ACK

DATA

HIZ

DATA (n)

DATA (n + 1)

ACK

DATA (n + 2)

HIZ

LSB

MSB

Address

SDA

SCL

MSB

L during Write

MSB

LSB

HIZ

ACK

Sub Address

ACK

CXA2094Q

Input level vs. Distortion characteristics 1 (MONO)

i
s

t
o

r
t
i
o

[
%

]

1.0

0.1

Input level vs. Distortion characteristics 2 (Stereo)

i
s

t
o

r
t
i
o

[
%

]

1.0

Input level [dB]

Input signal: Stereo L = R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
V

= 9V, 30kHz using LPF, ST mode

Measurement point: TVOUT-L/R

Input level vs. Distortion characteristics 3 (SAP)

i
s

t
o

r
t
i
o

[
%

]

1.0

Input level [dB]

Standard level (100%)

Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
V

= 9V, 30kHz using LPF, SAP mode

Measurement point: TVOUT-L/R

Standard level (100%)

Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
V

= 9V, 30kHz using LPF

Measurement point: TVOUT-L/R

CXA2094Q

Frequency [kHz]

i
n

[
d

]

Stereo LPF frequency characteristics

100

70 100

i
n

(
F

i
n

)

[
d

]

Frequency [kHz]

Main LPF and Sub LPF frequency characteristics

100

120

SAP frequency characteristics and group delay

r
o

l
a

[
µ

]

100

Gain

Group delay

3.8f

6.2f

Frequency [kHz]

i
n

[
d

]

Frequency [kHz]

Additional SAP frequency characteristics

t
p

t

l
e

l

[
m

r
m

]

500

100

1.0

100% modulation

30% modulation

10% modulation

1% modulation

0.1

CXA2094Q

Package Outline

Unit: mm

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER / PALLADIUM

PLATING

COPPER / 42 ALLOY

48PIN QFP (PLASTIC)

15.3 ± 0.4

12.0 0.1

+ 0.4

0.8

0.3 0.1

+ 0.15

± 0.12

2.2 0.15

+ 0.35

.
9

.
2

0.1 0.1

+ 0.2

.
5

0.15

0.15 0.05

+ 0.1

QFP-48P-L04

QFP048-P-1212-B

0.7g

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2094Q

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2094Q