CXB1577Q

E96Z24-PS

Post-Amplifier for Optical Fiber Communication Receiver

Description

The CXB1577Q achieves the 2R optical-fiber

communication receiver functions (Reshaping and

Regenerating) on a single chip. This IC is equipped

with the signal detection function, which is used to

enable TTL/ECL outputs. Also, the output disable

function performs the output shutdown. 3.3V/5.0V

can be used for the supply voltage.

Features

· Output disable function (TTL input)

· Signal detection function (TTL/ECL output)

· Supply voltage supports both 3.3V/5.0V

Applications

· SONET/SDH:

622.08Mbps

· Fibre Channel:

531.25Mbps

1.062Gbps

· Gigabit-Ethernet: 1.25Gbps

Absolute maximum Ratings

· Supply voltage

0.3 to +7

· Storage temperature

Tstg

65 to +150

°C

· Input voltage difference

Vdif

0 to +2

· SW input voltage

to V

· ECL output current

Q/SD-ECL

30 to 0

· TTL output current (High level)

SD-TTL

20 to 0

· TTL output current (Low level)

SD-TTL

0 to 20

Recommended Operating Conditions

· Supply voltage

3.3 ± 0.2/5 ± 0.25

· Termination voltage (for data)

1.8 to 2.2

· Termination voltage (for alarm 1,alarm 2)

VTA

· Termination resistance (for data)

46 to 56

· Termination resistance (for alarm 1)

RTA1

240 to 300

· Termination resistance (for alarm 2)

RTA2

460 to 560

· Operating temperature

40 to +85

°C

Structure

Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

40 pin QFP (Plastic)

CXB1577Q

Block Diagram and Pin Configuration

N.C.

I
S

.
C

VC1

SDB-ECL

SDB-TTL

SD-TTL

N.C.

CAP1B

CAP1

VC0

SD-ECL

peak hold

CXB1577Q

Pin Description

No.

3.3V

/ 5V

Negative power supply for ECL
output buffer.

Switches the identification
maximum voltage amplitude.
High voltage when open; the
identification maximum voltage
amplitude becomes 40mVp-p.
Low voltage when connected
to V

; the amplitude becomes

20mVp-p.

ODIS

(Open)

3.3V

/ 5V

(Open)

3.3V

/ 5V

Switches 3.3V/5V. Short this pin
to Vcc for 3.3V between Vcc and
V

. Leave this pin open for 5V

between Vcc and V

No connected.

Negative power supply for digital
block.

Negative power supply for analog
block.

Chip temperature monitor.

VC2

/1.7V

(Open)

N.C.

3.3V

/ 5V

3.3V

/ 5V

1.8V

/ 3.5V

Controls the output shutdown
function. High voltage when
open; the Q output is fixed to
Low. Low voltage when
connected to V

; the D input

results in the Q output with ECL
level. TTL level is also available.

Symbol

Typical pin
voltage

Equivalent circuit

Description

40k

60k

REF

10k

300

Positive power supply for digital block.

CXB1577Q

VC0

N.C.

CAP1B

CAP1

N.C.

0.9V

1.7V

0.9V

1.7V

Positive power supply for analog block.

No connected.

Switches 3.3V/5V. Short this pin
to Vcc for 3.3V between Vcc and
V

. Leave this pin open for 5V

between Vcc and V

Pins 15 and 16 connect a
capacitor which determines the
cut-off frequency for DC
feedback block.
Pins 17 and 18 are input pins
for limiting amplifier block. Input
the signal with AC coupled.

Negative power supply for analog
block.

Positive power supply for digital block.

No connected.

Connects a resistor for alarm
level setting.
Default voltage can be generated
without an external resistor by
shorting the V

I pin to V

Generates the default voltage
between UP and DOWN.
The voltage (8.0mV for input
conversion) can be generated
between UP and DOWN (Pins
22 and 23) as alarm setting level
by connecting this pin to V

1.3V

3.3V

/5V

3.3V

/5V

3.3V

/5V

200

7.5k

100p

200

7.5k

No.

Symbol

Typical pin
voltage

Equivalent circuit

Description

100

986

100

140.9

Negative power supply for digital
block.

/1.7V

(Open)

CXB1577Q

CAP2

1.8V

Connects a peak hold circuit
capacitor for alarm block.
470pF should be connected
to Vcc each.

CAP2 pin connects a peak
hold capacitor for alarm
level setting block.
CAP3 pin connects a peak
hold capacitor for limiting
amplifier signal.

200

5µA

10p

CAP3

1.8V

VC3

N.C.

1.7V

(Open)

3.3V

/5V

Switches 3.3V/5V. Short this pin
to Vcc for 3.3V between Vcc and
V

. Leave this pin open for 5V

between Vcc and V

200

5µA

10p

VC1

1.7V

(Open)

Switches 3.3V/5V. Short this pin
to Vcc for 3.3V between Vcc and
V

. Leave this pin open for 5V

between Vcc and V

No.

Symbol

Typical pin
voltage

Equivalent circuit

Description

Negative power supply for TTL
output buffer.

No connected.

Positive power supply for TTL
output buffer.

CXB1577Q

Supply current

Q/QB High output voltage

Q/QB Low output voltage

SD-ECL/SDB-ECL High output voltage

SD-ECL/SDB-ECL Low output voltage

SD-TTL/SDB-TTL High output voltage 1

SD-TTL/SDB-TTL High output voltage 2

SD-TTL/SDB-TTL Low output voltage

SW High input voltage

SW Low input voltage

SW High input current

SW Low input current

ODIS High input voltage

ODIS Low input voltage

ODIS High input current

ODIS Low input current

D/DB input resistance

Electrical Characteristics

DC Characteristics

Item

VOH

VOL

VOH-E

VOL-E

VOH-T1

VOH-T2

VOL-T

VIHSW

VILSW

IIHSW

IILSW

VIHOD

VILOD

IIHOD

IILOD

Rin

to VTT

Ta = 0 to +85°C

When Vcc V

= 5.0V,

510

to V

;

when Vcc V

= 3.3V,

270

to V

Ta = 0 to +85°C

IOH = 0.4mA,
V

= 3.3V,

Ta = 0 to +85°C

IOH = 0.4mA,
V

= 5V,

Ta = 0 to +85°C

IOL = 2mA
Ta = 0 to +85°C

at SW pin Open: High

at ODIS pin Open: High

1100

1860

1100

1890

+ 2.2

+ 2.4

0.5

100

+ 2.0

400

765

1020

860

1620

860

1650

+ 0.5

+ 0.8

1275

µA

Symbol

Min.

Typ.

Max.

Unit

Conditions

= GND, V

= 5V ± 5%, Ta = 40 to +85°C, VC0 to VC3 = open,

or V

= GND, V

= 3.3V ± 5%, Ta = 40 to +85°C, VC0 to VC3 = GND

CXB1577Q

AC Characteristics

VUP VDOWN = 100mV, Vin = 100mVp-p (single ended), SW pin: High, peak hold capacitance (CAP2,

CAP3 pins) of 470pF, connect V

I to V

VUP VDOWN = 100mV, Vin = 1Vp-p (single ended), SW pin: High, peak hold capacitance (CAP2, CAP3

pins) of 470pF, connect V

I to V

Vin = 50mVp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect V

I to V

Vin = 1Vp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect V

I to V

Maximum input voltage amplitude

Amplifier gain (excluding the output buffer)

Identification maximum voltage
amplitude of alarm level

SD/SDB hysteresis width

Alarm setting level for default

Q/QB rise time

Q/QB fall time

SD-TTL/SDB-TTL rise time

SD-TTL/SDB-TTL fall time

SD-ECL/SDB-ECL rise time

SD-ECL/SDB-ECL fall time

Propagation delay time

SD response assert time

SD response deassert time

SD response assert time for alarm
level default

SD response deassert time for alarm
level default

Item

Vmax

VmaxA1

VmaxA2

Vdef

TrQ

TfQ

TrSDT

TfSDT

TrSDE

TfSDE

TPD

Tas

Tdas

Tasd

Tdasd

single-ended input

SW pad: Low,
single-ended input

SW pad: Open High,
single-ended input

SW pin: Low,
at default alarm level

SW pin: Open High,
at default alarm level

UP/DOWN pin: open,
V

I = V

Differential voltage input

20% to 80%
50

to VTT

+ 0.8V to V

+ 2.0V

= 10pF

20% to 80%
When Vcc V

= 5.0V,

510

to V

when Vcc V

= 3.3V,

270

to V

1600

7.0

0.4

2.3

8.4

230

9.7

350

1.6

1.9

100

mVp-p

µs

Symbol

Min.

Typ.

Max.

Unit

Conditions

= GND, V

= 5V ± 5%, Ta = 40 to +85°C, VC0 to VC3 = open,

or V

= GND, V

= 3.3V ± 5%, Ta = 40 to +85°C, VC0 to VC3 = GND

CXB1577Q

DC Electrical Characteristics Measurement Circuit

N.C.

I
S

.
C

VC1

SDB-ECL

SDB-TTL

SD-TTL

N.C.

CAP1B

CAP1

VC0

SD-ECL

peak hold

5.0V/3.3V

ODIS

510

270
510

270

VTT

When V

= 5.0V: VC0 to VC3 = open

When V

= 3.3V: VC0 to VC3 = Vcc

CXB1577Q

AC Electrical Characteristics Measurement Circuit

0.047µF

N.C.

I
S

.
C

VC1

SDB-ECL

SDB-TTL

SD-TTL

N.C.

CAP1B

CAP1

VC0

SD-ECL

peak hold

470p

0.047µF

1µF

+2V

When V

= 3.0V: VC0 to VC3 = open

When V

= 1.3V: VC0 to VC3 = Vcc

Z0 = 50

3V/ 1.3V

Oscilloscope

input

Z0 = 50

Oscilloscope

Hi-Z input

EX1

CXB1577Q

Application Circuit

EX1

N.C.

I
S

.
C

VC1

SDB-ECL

SDB-TTL

SD-TTL

N.C.

CAP1B

CAP1

VC0

SD-ECL

peak hold

470p

0.047µF

When V

= 3.3V: VC0 to VC3 = Vcc

When V

= 5.0V: VC0 to VC3 = open

470p

VTT

Signal Generator

VTT

1µF

0.047µF

VTT

TTL

Input

VTT

2.0V

ECL Output

TTL Output

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXB1577Q

To IC interior

Fig. 1

Feedback frequency
response

Amplifier frequency
response

Frequency

i
n

Fig. 2

Notes on Operation

1. Limiting amplifier block

The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and

C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and

IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external

capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since

peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on

the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The

target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended

input is used, provide AC grounding by connecting Pin 17 to a capacitor which has the same capacitance as

capacitor C1.

R1 (internal): 1k

R2 (internal): 7.5k

f2: 3.4kHz

f1: 21Hz

C1 (external): 0.047µF

C2 (external): 1µF

CXB1577Q

2. Alarm block

In order to operate the alarm block, give the voltage difference between Pins 22 and 23 to set an alarm level
and connect the peak hold capacitor C3 shown in Fig. 3.
This IC has two setting methods of alarm level; one is to connect Pin 24 to V

and leave Pins 22 and 23 open

to set an alarm level default value (8mV for input conversion). The other is to connect Pin 24 to V

and set a

desired alarm level using the external resistors R

EX1

, R

EX2

and R

EX3

shown in Fig. 3. Connect R

EX1

between

Pins 22 and 23 or connect R

EX3

between Pin 23 and Vcc when less alarm level is desired to be set than its

default value; connect R

EX2

between Pin 22 and Vcc when more alarm level is desired to be set than its default

value. However, the Pin 22 voltage must be higher than that of Pin 23.
This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to
40mVp-p when Pin 3 is left open (High level) and it is set to 20mVp-p when Pin 3 is Low level. Therefore, the
noise margin can be increased by setting Pin 3 to Low level when the small signal is input. The relation of input
voltage and peak hold output voltage is shown in Fig. 5.
In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to
maintain a constant gain (design target value: 6dB) as shown in Fig. 4.
This IC is designed to externally have the capacitor C3, and the C3 value should be set so as to obtain desired
assert time and deassert time settings for the alarm signal.
The electrical characteristics for the SD response assert and deassert times are guaranteed only when
the waveforms are input as shown in the timing chart of Fig. 6.

EX1

: 100

(when the alarm level is set to 4mV for input conversion.)

EX2

: 8k

(when the alarm level is set to 10mV for input conversion.)

EX3

: 4k

(when the alarm level is set to 4mV for input conversion.)

C3: 470pF

The table below shows the alarm logic.

The table below shows the output disable function logic.

Peak Hold

SD-TTL

SD-ECL

SDB-ECL

SDB-TTL

Peak Hold

10p

From limiting amplifier

EX3

EX1

EX2

Ra1

986

IC interior

IC exterior

VCS

Ra2B

141

Ra2A

141

Ra1, Ra2A and Ra2B values are
typical values.

Optical signal input
state

Signal input

Signal interruption

Low level

High level

Low level

Optical signal input
state

ODIS: Open High

ODIS: Low

Fixed High

Data

Fixed Low

Data

Fig. 3

CXB1577Q

1. Q/QB output waveform

Ch. 1 = 400mV/div OFFSET = 1330mV, Ch. 2 = 400mV/div OFFSET = 1330mV, Timebase = 500ps/div

= GND

= 3.3V

= 2V

Ta = 27°C
D = 622Mbps
Vin = 10mVp-p
Single input
pattern: PRBS2

-1

Q/QB = 50

to V

Ch. 1 = 400mV/div OFFSET = 1330mV, Ch. 2 = 400mV/div OFFSET = 1330mV, Timebase = 200ps/div

= GND

= 3.3V

= 2V

Ta = 27°C
D = 1.25Gbps
Vin = 5mVp-p
Single input
pattern: PRBS2

-1

Q/QB = 50

to V

Ch. 1 = 400mV/div OFFSET = 1330mV, Ch. 2 = 400mV/div OFFSET = 1330mV, Timebase = 500ps/div

= GND

= 3.3V

= 2V

Ta = 27°C
D = 622Mbps
Vin = 5mVp-p
Single input
pattern: PRBS2

-1

Q/QB = 50

to V

Fig. 7

Fig. 8

Fig. 9

Example of Representative Characteristics

CXB1577Q

2. Bit error rate

3. Alarm level

622Mbps
1.0Gbps
1.25Gbps

Bit error rate vs. Data input level

Data input level [mVp-p]

1.5

2.5

3.5

4.5

= GND

= 3.3V

= 2V

Ta = 27°C
Single input
pattern: PRBS2

-1

Q/QB = 50

to V

i
t

e

r
r
o

r

r
a

t
e

Alarm level temperature

Ta [°C]

2.0

l
a

r
m

l
e

l

[
m

]

2.5

3.0

3.5

4.0

4.5

5.0

6.0

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

Up-Down = 200

EX1

)

5.5

Alarm level vs. R

EX1

UP-DOWN (REX1) [

]

l
a

r
m

l
e

l

[
m

]

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

Ta = 27°C
Differential input

Ch. 1 = 400mV/div OFFSET = 1330mV, Ch. 2 = 400mV/div OFFSET = 1330mV, Timebase = 200ps/div

= GND

= 3.3V

= 2V

Ta = 27°C
D = 1.25Gbps
Vin = 10mVp-p
Single input
pattern: PRBS2

-1

Q/QB = 50

to V

Fig. 10

Fig. 11

Fig. 12

Fig. 13

CXB1577Q

Alarm level supply voltage

[V]

3.0

2.0

Fig. 14

3.3

3.6

l
a

r
m

l
e

l

[
m

]

2.5

3.0

3.5

4.0

4.5

5.0

6.0

SW = H
SW = L

fin = 100Mbps
Ta = 27°C
Up-Down = 200

(REX1)

3.1

3.4

3.2

3.5

5.5

Alarm level temperature

Ta [°C]

11.0

l
a

r
m

l
e

l

[
m

]

11.5

12.0

12.5

13.0

13.5

14.0

15.0

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

-UP = 5k

EX2

)

14.5

Alarm level supply voltage

[V]

3.0

11.0

3.3

3.6

l
a

r
m

l
e

l

[
m

]

11.5

12.0

12.5

12.0

13.5

14.0

15.0

SW = H
SW = L

fin = 100Mbps
Ta = 27°C
V

-UP = 5k

EX2

)

3.1

3.4

3.2

3.5

14.5

Alarm level vs. R

EX2

-UP (R

EX2

) [

]

l
a

r
m

l
e

l

[
m

]

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

Ta = 27°C
Differential input

Alarm level temperature

Ta [°C]

2.5

l
a

r
m

l
e

l

[
m

]

3.0

3.5

4.0

4.5

5.0

6.0

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

-Down = 3k

EX3

)

5.5

Alarm level vs. R

EX3

-DOWN (R

EX3

) [

]

l
a

r
m

l
e

l

[
m

]

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

Ta = 27°C
Differential input

Fig. 15

Fig. 16

Fig. 17

Fig. 18

Fig. 19

CXB1577Q

Alarm level supply voltage

[V]

3.0

2.0

3.3

3.6

l
a

r
m

l
e

l

[
m

]

2.5

3.0

3.5

4.0

4.5

5.0

6.0

SW = H
SW = L

fin = 100Mbps
Ta = 27°C
V

-Down = 3k

EX3

)

3.1

3.4

3.2

3.5

5.5

Hyteresis width supply voltage

[V]

3.0

0.0

3.3

3.6

[
d

]

1.0

2.0

3.0

4.0

5.0

6.0

8.0

SW = H
SW = L

fin = 100Mbps
Ta = 27°C
Up, Down = Open
V

I = V

3.1

3.4

3.2

3.5

7.0

Hysteresis width vs. Alarm level

Alarm level [mV]

2.0

0.0

8.0

14.0

[
d

]

1.0

2.0

3.0

4.0

5.0

6.0

8.0

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

Ta = 27°C

4.0

10.0

6.0

12.0

7.0

Hysteresis width temperature

Ta [°C]

0.0

[
d

]

2.0

3.0

4.0

5.0

6.0

8.0

SW = H
SW = L

fin = 100Mbps
V

= 3.3V

Up, Down = Open
V

I = V

7.0

1.0

Alarm level vs. Data rate

fin [Mbps]

200

800

1400

l
a

r
m

l
e

l

[
m

]

SW = H
SW = L

= 3.3V

Ta = 27°C
Up, Down = Open
V

I = V

400

1000

600

1200

Hysteresis width vs. Data rate

fin [Mbps]

200

800

1400

[
d

]

SW = H
SW = L

= 3.3V

Ta = 27°C
Up, Down = Open
V

I = V

400

1000

600

1200

Fig. 20

Fig. 21

Fig. 22

Fig. 23

Fig. 24

Fig. 25

CXB1577Q

SD-ECL "H" level supply voltage

[V]

3.0

1100

3.3

3.6

"
H

"

l
e

l

[
m

]

1060

1020

980

940

900

860

SD-ECL
SDB-ECL

Ta = 27°C

3.1

3.4

3.2

3.5

SD-ECL "L" level temperature

Ta [°C]

100

SD-ECL
SDB-ECL

= 3.3V

1880

"
L

"

l
e

l

[
m

]

1840

1800

1760

1720

1680

SD-ECL "L" level supply voltage

[V]

3.0

1880

3.3

3.6

"
L

"

l
e

l

[
m

]

1840

1800

1760

1720

1680

SD-ECL
SDB-ECL

Ta = 27°C

3.1

3.4

3.2

3.5

SD-ECL "H" level temperature

Ta [°C]

100

SD-ECL
SDB-ECL

= 3.3V

1100

"
H

"

l
e

l

[
m

]

1060

1020

980

940

900

860

SD-TTL "H" level supply voltage

[V]

3.0

2.2

3.3

3.6

"
H

"

l
e

l

[
V

]

2.4

2.6

2.8

3.0

3.4

Ta = 27°C

3.1

3.4

3.2

3.5

3.2

SD-TTL "H" level temperature

Ta [°C]

100

= 3.3V

2.2

"
H

"

l
e

l

[
V

]

2.4

2.6

2.8

3.0

3.4

3.2

4. DC voltage

Fig. 26

Fig. 27

Fig. 28

Fig. 29

Fig. 30

Fig. 31

CXB1577Q

SD-TTL "L" level temperature

Ta [°C]

100

= 3.3V

200

"
L

"

l
e

l

[
m

]

250

300

350

400

SD-TTL "L" level supply voltage

[V]

3.0

200

3.3

3.6

"
L

"

l
e

l

[
m

]

250

300

350

400

Ta = 27°C

3.1

3.4

3.2

3.5

Q "H" level supply voltage

[V]

3.0

1100

3.3

3.6

"
H

"

l
e

l

[
m

]

1060

1020

980

940

900

860

Q-H
QB-H

Ta = 27°C

3.1

3.4

3.2

3.5

Q "H" level temperature

Ta [°C]

100

Q-H
QB-H

= 3.3V

1100

"
H

"

l
e

l

[
m

]

1060

1020

980

940

900

860

Q "L" level supply voltage

[V]

3.0

1860

3.3

3.6

"
L

"

l
e

l

[
m

]

1820

1780

1740

1700

1660

Q-L
QB-L

Ta = 27°C

3.1

3.4

3.2

3.5

1620

Q "L" level temperature

Ta [°C]

100

Q-L
QB-L

= 3.3V

"
L

"

l
e

l

[
m

]

1860

1820

1780

1740

1700

1660

1620

Fig. 32

Fig. 33

Fig. 34

Fig. 35

Fig. 36

Fig. 37

CXB1577Q

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER / PALLADIUM

42/COPPER ALLOY

PACKAGE STRUCTURE

PLATING

0.2g

QFP-40P-L01

QFP040-P-0707

40PIN QFP (PLASTIC)

9.0 ± 0.4

+ 0.4

0.3 0.1

1.5 0.15

+ 0.35

0.127 0.05

+ 0.1

(
8

.
0

)

DETAIL

0.1 0.1

+ 0.15

7.0 0.1

.
5

.
2

0.1

± 0.12

0.65

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

Package Outline

Unit: mm

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXB1577Q

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXB1577Q