CXP858P56A

E97738-PS

CMOS 8-bit Single Chip Microcomputer

Description

The CXP858P56A is a CMOS 8-bit microcomputer

which consists of A/D converter, serial interface,
timer/counter, time-base timer, closed caption decoder,
data slicer, on-screen display function, I

C bus

interface, PWM output, remote control reception
circuit, HSYNC counter and watchdog timer as well
as basic configuration like 8-bit CPU, PROM, RAM
and I/O port.

Also this IC provides a power-on reset function

and sleep function that enables to lower power
consumption.

The CXP858P56A is the PROM-incorporated version

of the CXP85856A with built-in mask ROM. This
provides the additional feature of being able to write
directly into the program (also into the OSD
character ROM or caption character ROM possible).
Thus, it is most suitable for evaluation use during
system development and for small-quantity production.

Features
· A wide instruction set (213 instructions) which covers various types of data

16-bit operation/multiplication and division/Boolean bit operation instructions

· Minimum instruction cycle

333ns at 12MHz operation

· Incorporated PROM

56K bytes (Programming)
4.5K bytes (OSD)
3K bytes (Caption)

· Incorporated RAM

2176 bytes (Excludes the closed caption decoder and on-screen display VRAM)

· Peripheral functions

A/D converter

8-bit 6-channel successive approximation method
(Conversion time of 26.7µs at 12MHz)

Serial interface

8-bit clock sync type, 1 channel

Timer

8-bit timer, 8-bit timer/counter, 19-bit time-base timer

Closed caption decoder

Incorporated data slicer,
conforming to FCC (EDS supported), 8

13 dots, 192 character types,

15 character colors, 4 lines

34 characters, italic, underline, vertical scrolling,

15 frame background colors/half blanking

On-screen display (OSD) function

16 dots, 192 character types, 15 character colors, 2 lines

24 characters,

8 frame background colors/half blanking,
15 background colors on full screen/half blanking,
edging and vertical scrolling for every line,
jitter elimination circuit,
sprite OSD, 12

16 dots, 1 screen, 8 colors for every dot

C bus interface

PWM output

8 bits, 8 channels

Remote control reception circuit

8-bit pulse measurement counter, 6-stage FIFO

HSYNC counter

2 channels

Watchdog timer

· Interruption

15 factors, 15 vectors, multi-interruption possible

· Standby mode

Sleep

· Package

64-pin plastic SDIP/QFP

urchase of Sony's I

C components conveys a license under the Philips I

C Patent Rights to use these components

in an I

C system, provided that the system conform to the I

C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin SDIP (PIastic)

64 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

CXP858P56A

EXL

SYN

VSYN

s s

LFC

I
CE

EEN

SPL

SER

I
AL

I
NT

UNI

I
T

UNT

I N

SCL

SDA1

SDA0

I
NT

UNI

I
T

CHDO

ESC

BASE

700

56K

BYT

SYST

2176

BYT

Vs s

XTAL

EXTAL

PWM

0`PW

POR

T A

PA0

PA7

PB0

PB6

PE0

PE2

I N

T C

POR

T B

POR

T C

POR

T D

POR

T E

POR

T F

I
T

LFC

Vpp

Block Diagram

CXP858P56A

Pin Assignment (Top View) 64-pin SDIP

PC3

PC2

PC1

PC0

EC/PD7

RMC/PD6

HS1/PD5

HS0/PD4

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

Vss

XTAL

EXTAL

PA5/AN5

PA4/AN4

PA3/AN3

PA2/AN2

PA1/AN1

PA0/AN0

CVss

LFC2

LFC1

VIN

Cap

INT1/PB6

PB5

PC4

PC5

PC6

PC7

PF0/PWM0

PF1/PWM1

PF2/PWM2

PF3/PWM3

PF4/SCL0/PWM4

PF5/SCL1/PWM5

PF6/SDA0/PWM6

PF7/SDA1/PWM7

PE0/TO

PE1

PE2/INT0

Vss

Vpp

EXLC

XLC

PB0

PB1

PB2

PB3

PB4

Note) 1. Vpp (Pin 46) must be connected to V

2. Vss (Pins 16 and 48) must be connected to GND.

3. MP (Pin 49) must be connected to GND.

CXP858P56A

Pin Assignment (Top View) 64-pin QFP

HS1/PD5

HS0/PD4

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

Vss

XTAL

EXTAL

PA5/AN5

PA4/AN4

PA3/AN3

PA2/AN2

PA1/AN1

PA0/AN0

CVss

PF3/PWM3

PF4/SCL0/PWM4

PF5/SCL1/PWM5

PF6/SDA0/PWM6

PF7/SDA1/PWM7

PE0//TO

PE1

PE2/INT0

Vss

Vpp

EXLC

XLC

PD6/RMC

PD7/EC

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PF0/PWM0

PF1/PWM1

PF2/PWM2

LFC2

LFC1

VIN

Cap

INT1/PB6

PB5

PB4

PB3

PB2

PB1

PB0

20 21 22 23 24 25 26 27 28 29 30 31 32

Note) 1. Vpp (Pin 40) must be connected to V

2. Vss (Pins 10 and 42) must be connected to GND.

3. MP (Pin 43) must be connected to GND.

(Port A)
8-bit I/O port. I/O
can be set in a unit
of single bits.
(8 pins)

(Port B)
7-bit I/O port. I/O can be set in a unit of single bits.
(7 pins)

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
Can drive 12mA
synk current.
(8 pins)

(Port E)
3-bit I/O port. I/O
can be set in a unit
of single bits.
(3 pins)

(Port F)
8-bit output port
and large current
(12mA) N-ch open
drain output.
Lower 4 bits are
medium drive voltage
(12V);upper 4 bits are

5V drive. (8 pins)

6-bit OSD display outputs. (6 pins)

CXP858P56A

Pin Description

Symbol

PA0/AN0

PA5/AN5

PA6/VSYNC

PA7/HSYNC

PB0 to PB5

PB6/INT1

PC0 to PC7

PD0/INT2

PD1/SCK

PD2/SO

PD3/SI

PD4/HS0

PD5/HS1

PD6/RMC

PD7/EC

PE0/TO

PE1

PE2/INT0

PF0/PWM0

PF3/PWM3

PF4/SCL0/PWM4
PF5/SCL1/PWM5

PF6/SDA0/PWM6
PF7/SDA1/PWM7

R, G, B, I, YS, YM

I/O/Analog input

I/O/Input

I/O

I/O/Input

I/O

I/O/Input

I/O/I/O

I/O/Output

I/O/Input

I/O/Output

I/O

I/O/Input

Output/Output

Output/I/O

Output

I/O

Description

Analog inputs to A/D converter. (6 pins)

OSD display vertical sync signal input.

OSD display horizontal sync signal input.

External interruption request input.
Active at the falling edge.

Serial clock I/O.

Serial data output.

Serial data input.

HSYNC counter (CH0) input.

HSYNC counter (CH1) input.

Remote control reception circuit input.

External event input for timer/counter.

Rectangular wave output for timer/counter.

Input for external interruption request.
Active at the falling edge.

8-bit PWM outputs.
(8 pins)

Transfer clock I/O for I

C bus interface.

(2 pins)

Transfer data I/O for I

C bus interface.

(2 pins)

CXP858P56A

Symbol

EXLC

XLC

VIN

Cap

LFC1, LFC2

EXTAL

XTAL

RST

Vpp

Vss

Input

Output

Input

Output

I/O

Input

OSD display clock oscillation I/O.
Oscillator frequency is determined by the external L and C.

External composite video signal input.
Input a 2Vp-p signal via a capacitor.

Connects a capacitor for the data slicer between Cap and CV

Connects a capacitor for the PLL circuit LPF between LFC1 and LFC2.

Positive power supply for data slicer.

GND for data slicer.

Connects a crystal for system clock oscillation. When an external
clock is supplied, input it to EXTAL and leave XTAL open.

System reset; active at Low level. I/O pin.
Outputs a Low level when the power is turned on and the power-on
reset function operates.

Test mode input. Must be connected to GND.

Positive power supply for internal PROM writing.
Under normal conditions, connect to V

Positive power supply.

GND. Connect two V

pins to GND.

I/O

Description

CXP858P56A

Input/Output Circuit Format for Pins

Data bus

Port A data

Port A direction

RD (Port A)

VSYNC, HSYNC

Input polarity

Schmitt input

"0" when reset

Port A data

Port A direction

Data bus

RD (Port A)

Port A function selection

"0" when reset

A/D converter

Input multiplexer

"0" when reset

Input
protection
circuit

Ports B, C data

Ports B, C direction

Data bus

RD (Ports B, C)

INT1

"0" when reset

Schmitt input

Port A

Port B

Port C

2 pins

6 pins

15 pins

Hi-Z

When reset

Circuit format

PA0/AN0

PA5/AN5

PB0 to PB5
PB6/INT1
PC0 to PC7

PA6/VSYNC
PA7/HSYNC

CXP858P56A

Port D data

Port D direction

Data bus

RD (Port D)

INT2, SI, HS0, HS1, RMC, EC

Large current 12mA

Schmitt input

"0" when reset

Port D data

Port D direction

Data bus

RD (Port D)

SCK only

Large current 12mA

SCK, SO

Serial output enable

Schmitt input

"0" when reset

Port E function selection

Port E direction

Port E data

Data bus

INT0

Schmitt input
only for PE2

RD (Port E)

"1" when reset

"1" when reset for PE0, 1

"0" when reset for PE2

"1" when reset for PE0, 1

Port D

Port E

6 pins

2 pins

3 pins

Hi-Z

PE0, PE1:

High level

PE2: Hi-Z

When reset

Circuit format

PD1/SCK
PD2/SO

PE0/TO
PE1
PE2/INT0

PD0/INT2
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC
PD7/EC

CXP858P56A

Port F data

Port F function selection

SCL, SDA

"1" when reset

C output enable

PWM4 to PWM7

BUS SW

To internal I

C pins

(SCL1 for SCL0)

Large current 12mA

SCL, SDA

C circuit)

Schmitt input

"0" when reset

Port F data

Port F function selection

PWM0 to PWM3

"1" when reset

"0" when reset

Large current 12mA

12V drive

Port F

4 pins

6 pins

2 pins

When reset

Circuit format

PF4/SCL0/PWM4
PF5/SCL1/PWM5
PF6/SDA0/PWM6
PF7/SDA1/PWM7

Hi-Z

Oscillation
halted

PF0/PWM0

PF3/PWM3

EXLC
XLC

R, G, B, I, YS, YM

Output becomes active
by data writing to output
polarity register.

Output polarity

"0" when reset

Oscillator control

EXLC

OSD display clock

XLC

CXP858P56A

and V

OUT

should not exceed V

+ 0.3V.

The large current output port is Port D (PD) and Port F (PF).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding those conditions may adversely
affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Medium drive output voltage

High level output current

High level total output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

Vpp

OUT

OUTP

OLC

Topr

Tstg

0.3 to +7.0

0.3 to +13.0

0.3 to +7.0

0.3 to +15.0

100

10 to +75

55 to +150

1000

600

°C

Incorporated PROM

PF0 to PF3 pins

Total of all output pins

Ports excluding large current
outputs (value per pin)

Large current output port
(value per pin)

Total of all output pins

SDIP-64P-01

QFP-64P-L01

Item

Symbol

Ratings

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V reference)

5.5

+ 0.3

0.3V

0.2V

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.5

4.5

0.7V

0.8V

0.4

0.3

This device does not enter the stop mode.

PA, PB, PC, PE0 to PE1, SCL0 to SCL1, SDA0 to SDA1 pins.

INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins.

Specifies only during external clock input.

and V

should be set to the same voltage.

Vpp and V

should be set to the same voltage.

Recommended Operating Conditions

(Vss = 0V reference)

Supply voltage

Data slicer supply
voltage

High level
input voltage

Low level
input voltage

Operating temperature

IHS

IHEX

ILS

ILEX

Topr

Guaranteed operation range for 1/2 and 1/4
frequency dividing clocks

Guaranteed operation range for 1/16
frequency dividing clock or sleep mode

Guaranteed data hold range for stop mode

EXTAL pin

Vpp

Vpp = V

CXP858P56A

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 3.0mA

= 4.5V, I

= 4.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 4.5V, I

= 12.0mA

High level
output voltage

Low level
output voltage

Input current

I/O leakage current

Open drain output
leakage current
(in N-ch Tr OFF state)

C bus switch

connection impedance
(in output Tr OFF state)

Supply current

Input capacitance

4.0

3.5

2.5

5.0

5.5

10.0

µA

120

µA

0.4

0.6

1.5

0.4

0.6

400

±10

µA

0.5

1.5

PA to PD, PE, R, G,
B, I, YS, YM

PA to PD, PE, R, G,
B, I, YS, YM,
PF0 to PF3, RST

PD, PF

PF4 to PF7
(SCL0, SCL1,
SDA0, SDA1)

EXTAL

RST

PA to PE, HSYNC,
VSYNC, R, G, B, I,
YS, YM, RST

PF0 to PF3

PF4 to PF7

SCL0: SCL1
SDA0: SDA1

= 5.5V, V

= 0.4V

= 5.5V,

= 0, 5.5V

= 5.5V, V

= 12.0V

= 5.5V, V

= 5.5V

= 4.5V

SCL0

= V

SCL1

= 2.25V

SDA0

= V

SDA1

= 2.25V

Stop mode

= 5.5V

Termination of 12MHz
crystal oscillation

= 5.5V

Sleep mode
V

= 5.5V

12MHz crystal oscillation
(C

= C

= 15pF)

PA to PE, SCL, SDA,
EXLC, EXTAL, VIN,
RST

1MHz clock
0V for no-measured pins

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

LOH

DDSL

DDST

CVDD

IHE

IHL

ILR

DC Characteristics

(Ta = 10 to +75°C, Vss = 0V reference)

Specifies RST pin only when the power-on reset circuit is selected with mask option.

For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage
current when non-resistance is selected.

When all output pins are left open. Specifies only when the OSD oscillation is halted.

This device does not enter the stop mode.

1/2 frequency dividing
clock operation V

= 5.5V

12MHz crystal oscillation
(C

= C

= 15pF)

CXP858P56A

AC Characteristics

(1) Clock timing

Indicates three values according to the contents of the clock control register (CLC: 00FE

) upper 2 bits

(CPU clock selection).

sys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

System clock frequency

System clock input
pulse width

System clock input
rise and fall times

Event counter input
clock pulse widtth

Event counter input clock
rise and fall times

XTAL
EXTAL

EXTAL

MHz

Item

Symbol

Condition

Min.

Max.

Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig 1, Fig 2
External clock drive

Fig. 3

37.5

sys

+ 50

Typ.

12.0

200

(Ta = 10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Fig. 1. Clock timing

EXTAL

0.4V

1/fc

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

OPEN

Fig. 3. Event count clock timing

0.2V

0.8V

CXP858P56A

(2) Serial transfer

(Ta = 10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCK cycle time

KCY

SCK

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

1000

8000/fc

400

4000/fc 50

100

200

100

200

100

SCK

SIK

KSI

KSO

SCK
High and Low level widths

SI input setup time
(for SCK

)

SI hold time
(for SCK

)

SCK

SO delay time

Symbol

Condition

Min.

Max.

Unit

Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

Fig. 4. Serial transfer timing

0.2V

0.8V

KCY

SIK

KSI

0.2V

0.8V

KSO

0.2V

0.8V

Output data

Input data

SCK

CXP858P56A

Resolution

Linearity error

Zero transition
voltage

Full-scale transition
voltage

Conversion time

Sampling time

Analog input voltage

CONV

SAMP

IAN

AN0 to AN5

Ta = 25°C
V

= 5.0V

Vss = 0V

4910

160/f

ADC

12/f

ADC

4970

±3

5030

Bits

LSB

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

(3) A/D converter characteristics

(Ta = 10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Linearity error

Analog input

Digital conversion value

Fig. 5. Definitions of A/D converter terms

Value at which the digital conversion value changes from

to 01

and vice versa.

Value at which the digital conversion value changes from

to FF

and vice versa.

ADC

indicates the below values due to the contents of bit 6

(CKS) of the A/D control register (ADC: 00F9

) and bits 7

(PCK1) and 6 (PCK0) of the clock control register (CLC:

00FE

00 (

= f

/2)

01 (

= f

/4)

11 (

= f

/16)

ADC

= f

ADC

= f

ADC

= f

/16

ADC

= f

CKS

PCK1, 0

0 (

/2 selection)

1 (

selection)

ADC

= f

ADC

= f

CXP858P56A

External interruption
High and Low level widths

Reset input Low level width

INT0
INT1
INT2

RST

32/fc

µs

Item

Symbol

Condition

Min.

Max.

Unit

RSL

Power supply rise time

Power supply cutt-off time

OFF

Power-on reset

Repeated power-on reset

0.05

Item

Symbol

Condition

Min.

Max.

Unit

(4) Interruption, reset input

(Ta = 10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

(5) Power-on reset

(Ta = 10 to +75°C, Vss = 0V reference)

0.2V

0.8V

INT0

INT1

INT2

(falling edge)

0.2V

4.5V

OFF

Take care when turning the power on.

Fig. 6. Interruption input timing

RSL

0.2V

RST

Fig. 7. RST input timing

Fig. 8. Power-on reset

CXP858P56A

(6) I

C bus timing

(Ta = 10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCL clock frequency

Bus-free time before starting transfer

Hold time for starting transfer

Clock Low level width

Clock High level width

Setup time for repeated transfers

Data hold time

Data setup time

SDA, SCL rise time

SDA, SCL fall time

Setup time for transfer completion

SLC

BUF

HD; STA

LOW

HIGH

SU; STA

HD; DAT

SU; DAT

SU; STO

SCL

SDA, SCL

SCL

SDA, SCL

4.7

4.0

4.7

4.0

4.7

250

4.7

100

300

kHz

µs

Symbol

Condition

Min.

Max.

Unit

The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.

Fig. 9. I

C bus transfer timing

SU; STO

SU; STA

HD; STA

SU; DAT

HIGH

HD; DAT

LOW

HD; STA

BUF

SDA

SCL

Fig. 10. I

C device recommended circuit

device

SDA0
(or SDA1)

SCL0
(or SCL1)

· A pull-up resistor (R

) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

· The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300

or less) can be used to reduce spike

noise caused by CRT flashover.

CXP858P56A

(7) OSD timing

(Ta = 10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

OSD clock frequency

HSYNC pulse width

HSYNC after-write
rise and fall times

VSYNC before-write
rise and fall times

OSC

HWD

HCG

VCG

EXLC
XLC

HSYNC

VSYNC

Fig. 12

Fig. 11

1.2

16.5

200

1.0

MHz

µs

Symbol

Condiiton

Unit

Min.

Max.

Fig. 11. OSD timing

0.8V

0.2V

HCG

HWD

HSYNC

For OSD I/O polarity register

(OPOL: 01FD

)

bit 7 at "0"

0.8V

0.2V

VCG

VSYNC

For OSD I/O polarity register

(OPOL: 01FD

)

bit 6 at "0"

Fig. 12. LC oscillation circuit connection

EXLC

XLC

The XLC series resistor can reduce the frequency of occurrence of the undersired radiation.

CXP858P56A

(8) Data slicer external circuit

(Ta = 10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

VIN pin coupling capacitance

Cap pin capacitance

PLL low-pass filter capacitance

Composite video signal input

VIN

Ccap

LPF

Video In

VIN

Cap

LFC1,
LFC2

VIN

0.1

4700

0.47

2.0

µF

Vp-p

Symbol

Min.

Unit

Typ.

Max.

Fig. 13. Data slicer external recommeded circuit

The B characteristic or more
of temperature characteristics
is recommended.

Remarks

LFC1

Cap

CVss

Ccap

Video In

VIN

LPF

5.0V

LFC2

[Recommended Constant]

= 220

(error: 5%; allowable power dissipation: 1/8W or more)

= 1M

(error: 5%; allowable power dissipation: 1/8W or more)

= 1200pF (ceramic), the B characteristic or more of temperature characteristics is recommended.

CXP858P56A

Appendix

Fig. 14. SPC700 Series recommended oscillation circuit

EXTAL

XTAL

EXTAL

XTAL

(i)

Manufacturer

KINSEKI LTD.

Model

fc (MHz)

(pF)

Rd (

)

Circuit

example

(i)

The XTAL series resistor can reduce the effect of electrostatic discharge noise.

RIVER ELETEC
CO., LTD.

12.0

HC-49/U03

HC-19/U (-S)

Option item

Mask

CXP858P56AS-1-

CXP858P56AQ-1-

Package

Program ROM capacity

Reset-pin pull-up resistor

Power-on reset circuit

Font data

64-pin plastic

SDIP/QFP

40/48/56K bytes

Existent/Non-existent

User specified

64-pin plastic

SDIP/QFP

PROM 56K bytes

Existent

User specified (PROM)

Products List

The font data for the one-time PROM version can be written in the same way as for the program.

CXP858P56A

Fig. 15. Characteristics curves

Supply current [mA]

vs. V

(fc = 12MHz, Ta = 25°C, Typical)

Supply voltage [V]

0.1

100

vs. fc

= 5V, Ta = 25°C, Typical)

1/16 frequency
dividing mode

Sleep mode

1/4 frequency
dividing mode

1/2 frequency
dividing mode

Sleep mode

1/16 frequency
dividing mode

1/4 frequency
dividing mode

1/2 frequency
dividing mode

System clock [MHz]

OSC

Parameter curve for OSD oscillation L vs. C

(Theoretically calculated value)

10MHz

12MHz

14MHz

100

Inductance [µ

100

, C

Capacitance [pF]

16MHz

C = C

//C

Supply current [mA]

CXP858P56A

Package Outline

Unit: mm

PACKAGE STRUCTURE

MOLDING COMPOUND

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

SONY CODE

EIAJ CODE

JEDEC CODE

SDIP-64P-01

42 ALLOY

SOLDER PLATING

EPOXY / PHENOL RESIN

64PIN SDIP (PLASTIC) 750mil

SDIP064-P-0750-A

57.6 0.1

+ 0.4

1.778

19.05

17.1 0.1

+ 0.3

0° to 15°

0.25 0.05

+ 0.1

0.5 MIN

4.75 0.1

+ 0.4

3 MIN

0.5 ± 0.1

0.9 ± 0.15

8.6g

SONY CODE

EIAJ CODE

JEDEC CODE

23.9 ± 0.4

20.0 0.1

0.4 0.1

+ 0.15

14.

0.15 0.05

+ 0.1

2.75 0.15

16.

0.1 0.05

+ 0.2

8 ±

± 0.12

0.15

+ 0.4

17.9 ±

0.4

+ 0.35

64PIN QFP(PLASTIC)

QFP64PL01

QFP064P1420

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER/PALLADIUM

42/COPPER ALLOY

PACKAGE STRUCTURE

PLATING

1.5g

1.0

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