1/10
September 2001
s
HIGH SPEED :
f
MAX
= 80MHz (TYP.) at V
CC
= 4.5V
s
LOW POWER DISSIPATION:
I
CC
=4
A(MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 393
DESCRIPTION
The M74HCT393 is an high speed CMOS DUAL
BINARY COUNTER fabricated with silicon gate
C
2
MOS technology.
This counter circuit contains independent ripple
carry counters and two 4-bit ripple carry binary
counters, which can be cascaded to create a
single divide by 256 counter.
Each 4-bit counter is incremented on the high to
low transition (negative edge) of the clock input,
and each has an independent clear input. When
CLEAR(CLR) is set to high, all four bits of each
counter are set to a low level. This enables count
truncation and allows the implementation of divide
by N counter configurations.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT393
DUAL BINARY COUNTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HCT393B1R
SOP
M74HCT393M1R
M74HCT393RM13TR
TSSOP
M74HCT393TTR
TSSOP
DIP
SOP
M74HCT393
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1 CLOCK
2 CLOCK
Clock Input Divide by 2
Section (HIGH to LOW
Edge-Triggered)
2, 12
1 CLEAR
2 CLEAR
Asynchronous Master
Reset Inputs
3, 4, 5, 6
1QA to 1QD Flip Flop Outputs
11, 10, 9, 8
2QA to 2QD Flip Flop Outputs
7
GND
Ground (0V)
14
Vcc
Positive Supply Voltage
INPUTS
OUTPUTS
CLOCK
CLEAR
QD
QC
QB
QA
X
H
L
L
L
L
L
COUNT UP
L
NO CHANGE
COUNT
OUTPUTS
QD
QC
QB
QA
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
M74HCT393
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LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
TIMING CHART
M74HCT393
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
C; derate to 300mW by 10mW/
C from 65
C to 85
C
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500(*)
mW
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
t
r
, t
f
Input Rise and Fall Time (V
CC
= 4.5 to 5.5V)
0 to 500
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5
to
5.5
2.0
2.0
2.0
V
V
IL
Low Level Input
Voltage
4.5
to
5.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-20
A
4.4
4.5
4.4
4.4
V
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
V
OL
Low Level Output
Voltage
4.5
I
O
=20
A
0.0
0.1
0.1
0.1
V
I
O
=4.0 mA
0.17
0.26
0.33
0.40
I
I
Input Leakage
Current
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
80
A
I
CC
Additional Worst
Case Supply
Current
5.5
Per Input pin
V
I
= 0.5V or
V
I
= 2.4V
Other Inputs at
V
CC
or GND
2.0
2.9
3.0
mA
M74HCT393
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AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6ns)
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/4 (per FLIP
FLOP)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
4.5
8
15
19
22
ns
t
PLH
t
PHL
Propagation Delay
Time
(CLOCK - QA)
4.5
19
30
38
45
ns
t
PLH
t
PHL
Propagation Delay
Time
(CLOCK - QB)
4.5
24
37
46
56
ns
t
PLH
t
PHL
Propagation Delay
Time
(CLOCK - QC)
4.5
28
43
54
65
ns
t
PLH
t
PHL
Propagation Delay
Time
(CLOCK - QD)
4.5
33
51
64
77
ns
t
PHL
Propagation Delay
Time
(CLEAR - Qn)
4.5
20
31
39
47
ns
f
MAX
Maximum Clock
Frequency
4.5
4.2
80
34
MHz
t
W(H)
t
W(L)
Minimum Pulse
Width (CLOCK)
4.5
8
15
19
22
ns
t
W(H)
Minimum Pulse
Width (CLEAR)
4.5
8
15
19
22
ns
t
REM
Minimum Removal
Time
4.5
5
6
8
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
Power Dissipation
Capacitance (note
1)
66
pF
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