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ST75951

V.34/56K ANALOG FRONT END

February 1999

TQFP48 (7 x 7 x 1.4mm)

(Full Plastic Quad Flat Pack)

ORDER CODE : ST75951

V.34/56K MODEM ANALOG FRONT-END (AFE)

16 BITS OVERSAMPLING SIGMA DELTA A/D
AND D/A CONVERTERS

85dB DYNAMIC RANGE

PROGRAMMABLE SAMPLING FREQUENCY

AUXILIARY ANALOG INPUT

MODEM SIDE OF SILICON DATA ACCESS AR-
RANGEMENT (DAA) INTEGRATED WITH AFE

KRYPTON ISOLATION INC. PATENTED
TECHNOLOGY ELIMINATE TRANSFORMER
OR LINEAR OPTO-COUPLERS

RING DETECT, LINE IN USE, CLID AND
OVER LOOP CURRENT DETECT

4 GPIO ASSOCIATED WITH 1 GENERAL
PURPOSE INTERRUPT OUTPUT

ANALOG AND DIGITAL LOOP-BACK MODE

SYNCHRONOUS SERIAL INTERFACE FOR
PROCESSORS DATA EXCHANGE

ON CHIP REFERENCE VOLTAGE

SINGLE POWER SUPPLY RANGE :
2.7V TO 5.25V

LOW POWER CONSUMPTION : 40mW @ 3.3V

TQFP48 PACKAGE

0.5

M CMOS PROCESS

DESCRIPTION
ST75951 is an analog front-end designed to im-
plement modems application up to 56Kbps.
ST75951 interfaces between DSP or HSP signals
and capacitive isolation barrier.
A complete D.A.A. is made with ST952 which inter-
faces between capacitive isolation barrier and the
telephone line.

It integrates a high resolution A/D and D/A
converter and incorporates Krypton Isolation
Inc. patented silicon D.A.A. technology.

ST75951

ST952

Digital

Tip

Ring

.
E

Figure 1

1/21

PIN LIST

Pin Number

Name

Type

Description

SCLK

Bit Shift Clock Output , SCLK = Coeff

I/O

Frame Synchronization Input (Slave)/Output (Master)

MCM

Master Clock Mode

Positive Digital Power Supply

DGND

Digital Ground (0V) (see Note1)

XTALOUT

Crystal Output

XTALIN

Crystal Input

HC1

Hardware Control Input

HC0

Hardware Control Input

PWRDWN

Power Down Input

M/S

Master/slave Control Input

RING

Ring Detect Output

GPI

General Purpose Interrupt Output

GPIO3

I/O

General Purpose Control Input/Output

GPIO2

I/O

General Purpose Control Input/Output

GPIO1

I/O

General Purpose Control Input/ Output

GPIO0

I/O

General Purpose Control Input/Output

REFP

Positive Reference Voltage

REFN

Negative Reference Voltage

AGND1

Analog Ground (0V) (see Note1)

ST952 Control Output

TSTA1

Reserved for test

CMP

Common Mode Voltage Input P

Receive Input

CMS

Common Mode Voltage Input S

TSTA2

Reserved for test

Transmit Output

AGND2

Analog Ground (0V) (see Note1)

Common Mode Voltage Output

Positive Analog Power Supply

AUXIN

Receive Auxiliary Analog Input Amplifier

Hardware Control Input for Clid/Off-hook

RESET

Reset Function to initialize the device

Timeslot Control Input

TSTD1

Reserved for Test (must be grounded in normal mode)

DIN

Serial Data Input

DOUT

Serial Data Output

Note 1 : Digital and Analog ground must be connected externally together.

.
T

ST75951

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PIN DESCRIPTION

1 - Power Supply (5 Pins)
1.1 - Power Supply (AV

, DV

)

These pins are the positive analog and digital
power supply input (2.7 to 5.25V).
In any case, the AV

voltage must always be higher

or equal to the DV

voltage (AV

1.2 - Analog Ground ( AGND1, AGND2)
These pins are the ground return of the DAC and
ADC analog section.

1.3 - Digital ground (DGND)
This pin is the ground return of the digital circuitry.
Note : In order to obtain published performances,
the analog AV

and digital DV

should be decou-

pled with respect to analog ground and digital
ground, respectively. Decoupling capacitors should
be as close as possible to the supplies pins. All
ground must be tied together. In the following sec-
tion the ground is referred as : GND.

2 - Serial Synchronous Interface (4 Pins)
2.1 Data (DIN, DOUT)
Digital data word input/output of the SSI (16 bits
data).

2.2 - Frame Synchronization (FS)
The frame synchronization is used to indicate that
the device is ready to send and receive data.
The data transfer begins on the falling edge of
frame-sync signal. The frame-SYNC can be gener-
ated internally or externally.

2.3 Serial Bit Clock (SCLK)
Clocks the digital data into DIN and out of DOUT
during the frame synchronization interval. The se-
rial bit clock is generated internally and equal to
MCLK/R (R programmed value in register 3). The
serial bit clock is a multiple of FS.

3 - Control Pins (10 Pins)
3.1 - Reset (RESET)
This pin initializes the internal counters and control
registers to their default value. A minimum low
pulse of 100ns is required to reset the chip.

3.2 - Power-Down (PWRDWN)
This input powers down the entire chip. In power
down mode the existing internally programmed
state is maintained. When power down is driven
high, full operation resumes after 1ms.

A software powerdown with wake-up on ring detect
is also provided with bit 4 in control register 3.

3.3 - Hardware Control (HC0, HC1)
These pins are used for hardware/software control
programmation of the device.

3.4 - Hardware Control (HM)
This pin is used for hardware/software control of
CLID/OFFHOOK function.

3.5 - Master/Slave (M/S)
When M/S = " 1 " the device is in master mode and
FS is generated internally otherwise the device is
in slave mode and Fs must be provided externally
and equal to SCLK*R / OVER.

3.6 - Timeslot Control (TS)
When TS = " 0 " the data are assigned to the
first timeslot (1st 16 bits after falling edge of FS)
otherwise the data are on the second timeslot
(bits 17 to 32).

3.7 - Control (D5, D6)
These pins transmit the control signals trough iso-
lation capacitors to ST952 which converts and
outputs the appropriate control signals.

3.8 - Master Clock Mode (MCM)
When MCM = " 1 ", we have
FS = Master Clock/[M

OVER] otherwise we

have FS = Master Clock/OVER and the M, Q
dividers are bypassed.

4 - General Purpose Input/Output Circuitry
4.1 - GPIO (4 Pins)
ST75951 offers 4 general purpose Input/Output
pins. The setting of the GPIO configuration is done
through the control register 1 and the signal level
of the GPIO are reflected in the feedback register 2.
At power on the GPIO are programmed as inputs.
In order to take into account the evolution of ST952,
thanks to the control register we will be able to send
a clock signal equal to F0/N (N programmed in
register 2) on GPIO0 and F0 on GPIO3.
When in DAA control hardware mode HM = 1, the
CLID and OFF-HOOK control is done by Pin GPIO1
(CLID) and GPIO2 (OFF-HOOK), otherwise when
HM = 0 then the CLID/OFF-HOOK control is done
by programming the adequate bit in the control
register 3 (Bit 2 , Bit 3, see Table 7).

ST75951

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4.2 - General Purpose Interrupt System (GPI)

The GPI will reflect any change of the GPIO'S
inputs or RING output when non-masked, so the
processor does not need to read the output control
word continuously. GPI level change tells the proc-
essor, one of the non-masked input pins level has
changed and he can read the control word. So
GPIO could extend the number of interrupt pins of
the processor.

5 - Ring

This pin is used for the Ring detect but also reports
the Line status, current limit.

6 - Digital Test Pin (TSTD1)

This pin is reserved for digital test purpose.

7 - Crystal (XTALIN , XTALOUT)

These pins must be tied to an external crystal or a
master clock generator (MCLK).

8 - Analog Interface (12 Pins)
8.1 - DAC and ADC Reference Voltage Output
(V

REFP

, V

REFN

)

These pins provide the positive and negative
reference Voltage used by the 16-bit converters.
The reference voltage, V

REF,

is the voltage difference

between the V

REFP

and V

REFN

outputs.

REFP

and V

REFN

should be externally decoupled

with respect to V

8.2 - Common Mode Voltage Output (V

)

This output pin is the common mode voltage
(AV

- AGND)/2 . This output must be decoupled

with respect to GND.

8.3 - Common Mode Voltage Input (V

CMP

, V

CMS

)

These input pins are the common mode voltage for
internal circuitry. They have to be connected exter-
nally to V

8.4 - Analog Transmit Output (D1 ,D2)
These pins are the output of the fully differential
converted analog signal, modulated at F0
(1MHz < F0 < 1.7MHz).
The digital data IN signal is converted in analog
signals (with (Sin X)/X compensation). Two ranges
of signal amplitude have to be considered ; modem
application with dynamic up to 2.5V

with maxi-

mum performances SNDR = 83dB, voice applica-
tion with dynamic up to 3.2V

differential

(SNDR = 75dB).
The transmit output stage can be programmed to
+2dB gain, 0db gain, 6dB or infinite attenuation.

8.5 - Analog Receive Inputs (D3, D4)
These pins are the differential analog inputs. These
analog inputs are presented to the F0 demodulator
and the sigma-delta modulator. The analog input
peak-to-peak differential signal range must be less
than 2.5 V

. The gain of the receive stage is

programmable to 0dB or 6dB.

8.6. - Analog Test Pin (TSTA1, TSTA2)
These pins are reserved for analog test purpose.

8.7 Analog Auxiliary Receive Inputs (AUXIN)
This pin is the auxiliary analog input. This analog
input is presented to the analog modulator. The
analog input peak-to-peak signal range must be
less than 1.25 V

. The gain of the receive stage

is 0dB.

PIN DESCRIPTION (continued)

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