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January 2005
STQ3NK50ZR-AP
STD3NK50Z - STD3NK50Z-1
N-CHANNEL 500V - 2.8
- 2.3A TO-92/DPAK/IPAK
Zener-Protected SuperMESHTM MOSFET
Table 1: General Features
s
TYPICAL R
DS
(on) = 2.8
s
EXTREMELY HIGH dv/dt CAPABILITY
s
ESD IMPROVED CAPABILITY)
s
100% AVALANCHE TESTED
s
NEW HIGH VOLTAGE BENCHMARK
s
GATE CHARGE MINIMIZED
DESCRIPTION
The SuperMESHTM series is obtained through an
extreme opyimization of ST's well established strip
based PowerMESHTM layout. In addition to push-
ing on-resistance significatly down, special care is
taken to ensure a very good dv/dt capability for the
most demanding application. Such series comple-
ments ST full range of high voltage MOSFETs
icluding revolutionary MDmeshTM products
APPLICATIONS
s
AC ADAPTORS AND BATTERY CHARGERS
s
SWITH MODE POWER SUPPLIES (SMPS)
s
LIGHTING
Table 2: Order Coder
Figure 1: Package
Figure 2: Internal Schematic Diagram
TYPE
V
DSS
R
DS(on)
I
D
Pw
STQ3NK50ZR-AP
STD3NK50Z
STD3NK50Z-1
500 V
500 V
500 V
3.3
3.3
3.3
0.5 A
2.3 A
2.3 A
3 W
45 W
45 W
3
2
1
TO-92 (Ammopak)
IPAK
1
3
DPAK
SALES TYPE
MARKING
PACKAGE
PACKAGING
STQ3NK50ZR-AP
Q3NK50ZR
TO-92
AMMOPAK
STD3NK50Z
D3NK50Z
DPAK
TAPE & REEL
STD3NK50Z-1
D3NK50Z
IPAK
TUBE
Rev. 2
STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
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Table 3: Absolute Maximum ratings
( ) Pulse width limited by safe operating area
(1)
I
D
2 di/dt
200A/s, V
DD
V
(BR)DSS
Table 4: Thermal Data
(#) When mounted on 1inch FR4, 2 Oz copper board.
Table 5: Avalanche Characteristics
Table 6: GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in-back-to-back Zener diodes have specifically been designed to enchance not only the device's
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the
usage of external components.
Symbol
Parameter
Value
Unit
DPAK/IPAK
TO-92
V
DS
Drain-source Voltage (V
GS
= 0)
500
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
500
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuous) at T
C
= 25C
2.3
0.5
A
I
D
Drain Current (continuous) at T
C
= 100C
1.45
0.32
A
I
DM
( )
Drain Current (pulsed)
9.2
2
A
P
TOT
Total Dissipation at T
C
= 25C
45
3
W
Derating Factor
0.36
0.025
W/C
V
ESD(G-S)
Gate source ESD (HBM-C=100 pF, R= 1.5K
)
2000
V
dv/dt (1)
Peak Diode Recovery voltage slope
4.5
V/ns
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
C
DPAK
IPAK
TO-92
Unit
Rthj-case
Thermal Resistance Junction-case Max
2.77
--
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
50 (#)
100
120
C/W
Rthj-lead
Thermal Resistance Junction-lead Max
--
--
40
C/W
T
l
Maximum Lead Temperature For Soldering Purpose
275
260
C
Symbol
Parameter
Max. Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
2.3
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 50 V)
120
mJ
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs= 1mA (Open Drain)
30
V
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
ELECTRICAL CHARACTERISTICS (T
CASE
=25C UNLESS OTHERWISE SPECIFIED)
Table 7: On/Off
Table 8: Dynamic
Table 9: Source Drain Diode
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 1 mA, V
GS
= 0
500
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 C
1
50
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
10
A
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 50 A
3
3.75
4.5
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 1.15 A
2.8
3.3
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
= 15 V
,
I
D
= 1.15 A
1.5
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
280
42
8
pF
pF
pF
C
oss eq.
(3)
Equivalent Output
Capacitance
V
GS
= 0V, V
DS
= 0V to 400 V
27.5
pF
t
d(on)
t
r
t
d(off)
t
f
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
V
DD
= 250 V, I
D
= 1.15 A
R
G
= 4.7
V
GS
= 10 V
(see Figure 19)
8
13
24
14
ns
ns
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 400 V, I
D
= 2.3 A,
V
GS
= 10V
(see Figure 22)
11
2.5
5.6
15
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
2.3
9.2
A
A
V
SD
(1)
Forward On Voltage
I
SD
= 2.3 A, V
GS
= 0
1.6
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
=2.3 A, di/dt = 100 A/s
V
DD
= 40V, T
j
= 25C
(see Figure 20)
250
745
6
ns
C
A
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
=2.3A, di/dt = 100 A/s
V
DD
= 40V, T
j
= 150C
(see Figure 20)
300
960
6.2
ns
C
A
STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
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Figure 3: Safe Operating Area For TO-92
Figure 4: Safe Operating Area For DPAK / IPAK
Figure 5: Output Characteristics
Figure 6: Thermal Impedance TO-92
Figure 7: Thermal Impedance For DPAK / IPAK
Figure 8: Transfer Characteristics
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Figure 9: Transconductance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 11: Static Drain-Source On Resistance
Figure 12: Capacitance Variations
Figure 13: Normalized Gate Threshold Voltage
vs Temperature
Figure 14: Source-Drain Forward Characteris-
tics
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