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April 2003
STD3NM50
STD3NM50-1
N-CHANNEL 500V - 2.5
- 3A DPAK/IPAK
Zener-Protected MDmeshTMPower MOSFET
s
TYPICAL R
DS
(on) = 2.5
s
HIGH dv/dt AND AVALANCHE CAPABILITIES
s
IMPROVED ESD CAPABILITY
s
LOW INPUT CAPACITANCE AND GATE
CHARGE
s
LOW GATE INPUT RESISTANCE
s
TIGHT PROCESS CONTROL AND HIGH
MANUFACTORING YIELDS
DESCRIPTION
The MDmeshTM is a new revolutionary MOSFET
technology that associates the Multiple Drain pro-
cess with the Company's PowerMESHTM horizontal
layout. The resulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company's proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar completition's products.
APPLICATIONS
The MDmeshTM family is very suitable for increase
the power density of high voltage converters allow-
ing system miniaturization and higher efficiencies.
ABSOLUTE MAXIMUM RATINGS
()Pulse width limited by safe operating area
TYPE
V
DSS
R
DS(on)
I
D
STD3NM50
STD3NM50-1
500V
500V
< 3
< 3
3 A
3 A
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
500
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
500
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuous) at T
C
= 25C
3
A
I
D
Drain Current (continuous) at T
C
= 100C
1.89
A
I
DM
(
q
)
Drain Current (pulsed)
12
A
P
TOT
Total Dissipation at T
C
= 25C
46
W
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=15K
)
4
KV
Derating Factor
0.37
W/C
dv/dt(1)
Peak Diode Recovery voltage slope
15
V/ns
T
stg
Storage Temperature
65 to 150
C
T
j
Max. Operating Junction Temperature
150
C
(1)I
SD
<3A, di/dt<400A/s, V
DD
<V
(BR)DSS
, T
J
<T
JMAX
1
3
DPAK
TO-252
3
2
1
IPAK
TO-251
INTERNAL SCHEMATIC DIAGRAM
STD3NM50/STD3NM50-1
2/10
THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (T
CASE
= 25 C UNLESS OTHERWISE SPECIFIED)
OFF
ON (1)
DYNAMIC
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
Rthj-case
Thermal Resistance Junction-case Max
2.73
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300
C
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
1
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 50 V)
130
mJ
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 1 mA, V
GS
= 0
500
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
1
A
V
DS
= Max Rating, T
C
= 125 C
10
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
5
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250A
3
4
5
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 1.5A
2.5
3
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 3 A
0.7
S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
140
pF
C
oss
Output Capacitance
40
pF
C
rss
Reverse Transfer
Capacitance
4
pF
R
G
Gate Input Resistance
f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
4
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STD3NM50/STD3NM50-1
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the
usage of external components.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
Turn-on Delay Time
Rise Time
V
DD
= 250V, I
D
= 1.5A
R
G
= 4.7
V
GS
= 10V
(see test circuit, Figure 3)
7
ns
t
r
10
ns
Q
g
Total Gate Charge
V
DD
= 400V, I
D
= 3A,
V
GS
= 10V
5.5
nC
Q
gs
Gate-Source Charge
2.5
nC
Q
gd
Gate-Drain Charge
2.4
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
r(Voff)
Off-voltage Rise Time
V
DD
= 480V, I
D
= 3A,
R
G
= 4.7
,
V
GS
= 10V
(see test circuit, Figure 5)
8
ns
t
f
Fall Time
9
ns
t
c
Cross-over Time
15
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
Source-drain Current
3
A
I
SDM
(2)
Source-drain Current (pulsed)
12
A
V
SD
(1)
Forward On Voltage
I
SD
= 3A, V
GS
= 0
1.5
V
t
rr
Reverse Recovery Time
I
SD
= 3A, di/dt = 100A/s,
V
DD
= 100 V, T
j
= 25C
(see test circuit, Figure 5)
210
ns
Q
rr
Reverse Recovery Charge
790
nC
I
RRM
Reverse Recovery Current
7.5
A
t
rr
Reverse Recovery Time
I
SD
= 3A, di/dt = 100A/s,
V
DD
= 100 V, T
j
= 150C
(see test circuit, Figure 5)
282
ns
Q
rr
Reverse Recovery Charge
1.1
C
I
RRM
Reverse Recovery Current
7.7
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs= 1mA (Open Drain)
30
V
STD3NM50/STD3NM50-1
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Static Drain-source On Resistance
Transconductance
Transfer Characteristics
Output Characteristics
Safe Operating Area For DPAK / IPAK
Thermal Impedance For DPAK / IPAK
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STD3NM50/STD3NM50-1
Normalized BVdss vs Temperature
Source-drain Diode Forward Characteristics
Normalized Gate Threshold Voltage vs Temp.
Capacitance Variations
Gate Charge vs Gate-source Voltage
Normalized On Resistance vs Temperature
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