1/3
DATA BRIEF
September 2005
STi5300
High-performance set-top box decoder
Rev. 1
DESCRIPTION
The new STi5300 MPEG-2 decoder from ST
provides a step-change in performance for pay TV
set-top boxes and digital video recorders.
Delivering 1.33 GOPS of processing power
through an ST230 VLIW CPU running at 333 MHz,
ST has ensured that manufacturers' investment in
new products is protected as the STi5300 can
easily accommodate today's interactive software,
and provides a platform that can support the even
more demanding applications of the future. Both
Linux and OS21 operating systems are supported,
and an MMU provides support for virtual memory
management.
The STi5300's power comes from the VLIW
architecture of the ST230 CPU. This allows four
instructions to be executed at each CPU cycle,
dramatically increasing performance. By
maintaining pin compatibility with the STi5100,
manufacturers can make use of the STi5300 with
minimal hardware redesign.
Package (27 x 27 PBGA 336 package)
Figure 1. STi5300 low-cost interactive set-top box
xxxx
STi5300
Transport
stream in
VCR
PSTN
QPSK ZIF Rx
STV0299
Smart
Cards
Smart
cards
Flash
IR Tx/Rx
128 Mbit
DDR
RGB
CVBS/YC
SiLabs
DAA
Transport
stream in
QPSK ZIF Rx
HDD
USB
port
(Optional)
and
STB6000
STV0299
and
STB6000
STI5300
2/3
FEATURES
ST231 VLIW host CPU
333 MHz, 32 Kbyte ICache,
32 Kbyte DCache
up to 1.333 GOPs at 333 MHz
dynamic memory management through MMU
Unified memory interface
Package 27 mm x 27 mm PBGA336
footprint optimized for 2 layer PCBs
Dual transport stream merger
supports DVB and DIRECTV
integrated DES-ECB, DVB and ICAM
descramblers
NDS RASP compliant
low-cost DVB-CI and Cable Card support
MPEG-2 MP@ML video decoder
trick modes including smooth fast forward
and rewind
Graphics/display
4 display planes
2, 4 and 8 bpp CLUT graphics, 256 x 30 bits
(AYCBCr) CLUT entries
16 bpp true color graphics,
alpha blending, antialiasing, antiflutter,
antiflicker filters
PAL/NTSC/SECAM encoder
RGB, CVBS, Y/C and YUV outputs with
10-bit DACs
encoding of CGMS, Teletext, WSS, VPS,
close caption
Audio subsystem
MPEG-1 layers I/II, MP3
Dolby
Digital decoding
Dolby Pro Logic
compatible output
PCM input, mixing and sample rate
conversion
SRS/TruSurroundXT
virtual surround sound
simultaneous MPEG audio decode and
output of Dolby streams
On-chip peripherals
4 ASCs (UARTs) with Tx and Rx FIFOs
6 parallel 8-bit I/O banks
2 smartcard interfaces and clock generators
3 SSCs for I
2
C/SPI master/slave interfaces
SiLabs line side (DAA) interface
USB 1.1/2.0 host, OHCI/EHCI compliant
DiSEqC 2.0
TM
interface
Enhanced security
PART NUMBERING
Table 1. Order codes
REVISION HISTORY
Table 2. Revision history
Part Number
Description
STi5300ZUA
Development version
STi5300AUA
Basic DVB
STi5300-Mboard
Development platform
STi5300-DVB
Software reference tree
Date
Revision
Description of changes
September-2005
1
First issue
3/3
STI5300
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
PDF 
ZIP