STV1602A
SERIAL INTERFACE TRANSMISSION DECODER
December 1992
28
29
30
31
32
33
34
35
18
17
16
15
14
13
12
11
10
27
26
25
24
23
22
21
20
19
36
1
2
3
4
5
6
7
8
9
37
D0
D1
D2
D3
D4
D5
D6
D8
D7
QFS
CX
GND
MON
ADS
DIX
DIY
DPR
FV
ESO
SY
GND
SX
QSW
TN1
D9
V
EE
V
EE
GND
AIX
AIY
RSE
EVR
SYN
PCK
GND
V
EE
ESI
1601A-01.EPS
PIN CONNECTIONS
PGA37
(Ceramic Package)
ORDER CODE : STV1602A
BUILT-IN AUTOMATIC EQUALIZER FOR UP TO
30dB ATTENUATION AT 135MHz (TYPICALLY
300m OF HIGH-GRADE COAXIAL CABLE), PLL
CIRCUIT FOR RECLOCKING, AND SERIAL-PAR-
ALLEL CONVERSION CIRCUIT.
THIS SERIAL TRANSMISSION DECODER RE-
QUIRES ONLY FEW EXTERNAL COMPONENTS.
OTHER RELATED IC's INCLUDE :
.
STV1601A, A SERIAL TRANSMISSION EN-
CODER (PARALLEL-TO-SERIAL CONVER-
SION)
.
STV1389AQ COAXIAL CABLE DRIVER
STRUCTURE
.
Hybrid IC
APPLICATIONS
SERIAL DATA TRANSMISSION DECODER
.
100 to 270 Mb/s
APPLICATIONS EXAMPLES
.
Serial data transmission of digital television
signals 525-625 lines
.
4:2:2 component 270Mb/s (10-bit)
.
4*fsc PAL composite 177Mb/s (10-bit)
.
4*fsc NTSC Composite 143Mb/s (10-bit)
FUNCTIONS
.
Cable equalizer
(maximum gain : 30dB at 135MHz)
.
PLL for serial clock generation
.
Reclocked
repeater
output
(active
loop
through)
.
Descrambler : modulo-2 multiplication by
G(x) = (x
9
+ x
4
+ 1) (x + 1)
.
Parallel-to-serial conversion
.
Sync monitor output
.
Eye pattern monitoring
.
Input signal detector
DESCRIPTION
The STV1602A is a Hybrid IC decoder which con-
verts serial data coming from a serial transmission
line into parallel data.
1/22
PIN DESCRIPTION
Pin
N
o
Symbol
Equivalent Circuit
Description
I/O
Standard
Min. Typ. Max. Unit
3
SY
Reclocked serial data output
in differential mode.
SX and SY are disabled
when TN1 is set High.
In this case, SX is set High
and SY is set Low
H
L
O
-1.6
-2.4
V
V
4
SX
5
QSW
(GND)
To be connected to GND
I
36
FV
Adjustment of VCO Free
running frequency : V
EE
level
gives the lowest frequency.
To adjust it, set TN1 High.
I
1
ESO
Output of phase comparator
: must be connected to ESI
with the shortest distance
O
-3.2
V
1602A-01.TBL
GND
EE
V
V
R3
30
30
2k
2k
3
4
145
1602A-02.EPS
GND
EE
V
1
2k
1k
1k
2k
1602A-04.EPS
GND
EE
V
36
5
1k
10k
10k
1602A-03.EPS
STV1602A
2/22
PIN DESCRIPTION (continued)
Pin
N
o
Symbol
Equivalent Circuit
Description
I/O
Standard
Min. Typ. Max. Unit
9
to
18
D9
to
D0
Parallel data output
H
L
O
-0.8
-1.6
V
V
19
PCK
Parallel clock output (rising
edge at data center)
H
L
O
-0.8
-1.6
V
V
21
EVR
Data output reference
potential
O
-1.2
V
26
AIX
Equalizer differential input
I
-2.0
V
25
AIY
28
NC
To be left open
I
-4.6
V
29
CX
Equalizer detector output;
Input signal :
absent
present
O
-2.4
-2.0
V
V
1602A-02.TBL
GND
EE
V
21
9
18
600
600
300
210
210
V
R3
1602A-05.EPS
GND
EE
V
10k
10k
26
300
3k
4k
4k
25
1602A-06.EPS
GND
EE
V
29
28
16k
2k
2k
1k
2k
1602A-07.EPS
STV1602A
3/22
PIN DESCRIPTION (continued)
Pin
N
o
Symbol
Equivalent Circuit
Description
I/O
Standard
Min. Typ. Max. Unit
31
MON
Equalizer monitor output.
Connect 75
resistor
between MON-GND.
Observe using a 50
input
oscilloscope at the 75
coaxial cable.
O
15
mV
(pp)
32
ADS
Serial data input selection
High : Digital input DIX/DIY
Low : Equalizer input
AIX/AIY
H
L
I
-0.5
-5
V
V
33
DIX
Serial data digital differential
input
I
34
DIY
Selected when ADS is High.
H
L
-1.0
-1.6
V
V
1602A-03.TBL
GND
EE
V
31
V
R3
500
1k
500
500
1602A-08.EPS
GND
E E
V
V
R3
V
R2
?
32
2k
2k
2k
1602A-09.EPS
EE
V
V
R3
33
34
V
R1
GND
500
500
500
1602A-10.EPS
STV1602A
4/22
PIN DESCRIPTION (continued)
Pin
N
o
Symbol
Equivalent Circuit
Description
I/O
Standard
Min. Typ. Max. Unit
37
ESI
PLL error signal input : must
be connected to ESO with
the shortest distance
i
-3.2
V
6
TN1
Serial data input activation
High : Input disabled (VCO
free running condition).
Low : Input enabled.
During switch-on phase, by
temporarily hold High for
quick start-up
I
-1.0
-4.0
V
V
20
SYN
State changes at each TRS
Sync word
3FFH 000H 000H
H
L
O
-1.0
-4.0
V
V
1602A-04.TBL
EE
V
GND
37
2k
1602A-11.EPS
EE
V
GND
6
4k
12k
2k
20k
1602A-12.EPS
V
CC
GND
2k
4k
2k
E E
V
20
1602A-13.EPS
STV1602A
5/22
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