1/27
s
OPERATING FROM V
CC
= 3.0 V to 5.0 V
s
SPEAKER: Mono, THD+N @ 1 kHz is 1%
Max @ 1 W into 8
BTL
s
HEADSET: Stereo, THD+N @ 1 kHz is 0.5%
Max. @ 85 mW into 32
BTL
s
VOLUME CONTROL: 32-step digital
volume control
s
OUTPUT MODE: Eight different selections
s
Ultra low pop-and-click
s
Low Shutdown Current (0.1 A, typ.)
s
Thermal Shutdown Protection
s
FLIP-CHIP Package 18 X 300 m Bumps
DESCRIPTION
The TS4855 is a complete low power audio
amplifier solution targeted at mobile phones. It
integrates, into an extremely compact flip-chip
package, an audio amplifier, a speaker driver, and
a headset driver.
The Audio Power Amplifier can deliver 1.1 W
(typ.) of continuous RMS output power into an 8
speaker with a 1% THD+N value. To the headset
driver, the amplifier can deliver 85 mW (typ.) per
channel of continuous average power into stereo
32
bridged-tied load with 0.5% THD+N @ 5 V.
This device features a 32-step digital volume
control and 8 different output selections. The
digital volume and output modes are controlled
through a three-digit SPI interface bus.
APPLICATIONS
Mobile Phones
ORDER CODE
J = Flip Chip Package - only available in Tape & Reel (JT))
PIN CONNECTIONS (top view)
Part Number
Temperature
Range
Package
J
TS4855IJT
-40, +85C
Pin Out (top view)
TS4855IJT - Flip Chip
TS4855
LOUDSPEAKER & HEADSET DRIVER
WITH VOLUME CONTROL
April 2003
TS4855
Application Information for a Typical Application
2/27
1 APPLICATION INFORMATION FOR A TYPICAL APPLICATION
External component descriptions
Component
Functional Description
C
in
This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the
amplifier's input terminals. Cin also creates a highpass filter with the internal input impedance Zin at
Fc = 1 / (2
x Zin x Cin).
C
s
This is the Supply Bypass capacitor. It provides power supply filtering.
C
B
This is the Bypass pin capacitor. It provides half-supply filtering.
SPI Bus Interface
TS4855
3/27
2 SPI BUS INTERFACE
2.1 Pin Descriptions
2.2 SPI Operation Description
The serial data bits are organized into a field
containing 8 bits of data as shown in
Table 1
. The
DATA 0 to DATA 2 bits determine the output
mode of the TS4855 as shown in
Table 2
. The
DATA 3 to DATA 7 bits determine the gain level
setting as illustrated by
Table 3
. For each SPI
transfer, the data bits are written to the DATA pin
with the least significant bit (LSB) first. All serial
data are sampled at the rising edge of the CLK
signal. Once all the data bits have been sampled,
ENB transitions from logic-high to logic low to
complete the SPI sequence. All 8 bits must be
received before any data latch can occur. Any
excess CLK and DATA transitions will be ignored
after the height rising clock edge has occurred.
For any data sequence longer than 8 bits, only the
first 8 bits will get loaded into the shift register and
the rest of the bits will be disregarded.
(SD = Shut Down Mode,
P
HS
= Non Filtered Phone In HS, P
IHF
= External High Pass Filtered Phone In IHF)
Pin
Functional Description
DATA
This is the serial data input pin
CLK
This is the clock input pin
ENB
This is the SPI enable pin active at high level
Table 1: Bit Allocation
DATA
MODES
LSB
DATA 0
Mode 1
DATA 1
Mode 2
DATA 2
Mode 3
DATA 3
gain 1
DATA 4
gain 2
DATA 5
gain 3
DATA 6
gain 4
MSB
DATA 7
gain 5
Table 2: Output Mode Selection
Output
Mode #
DATA 2
DATA 1
DATA 0
SPKR
out
R
out
L
out
0
0
0
0
SD
SD
SD
1
0
0
1
+12dBxP
IHF
SD
SD
2
0
1
0
MUTE
G1xP
HS
G1xP
HS
3
0
1
1
+12dBxP
IHF
G1xP
HS
G1xP
HS
4
1
0
0
MUTE
G2xR
in
G2xL
in
5
1
0
1
+12dBxP
IHF
G2xR
in
G2xL
in
6
1
1
0
MUTE
G1xP
HS
+
G2xR
in
G1xP
HS
+
G2xL
in
7
1
1
1
+12dBxP
IHF
G1xP
HS
+
G2xR
in
G1xP
HS
+
G2xL
in
TS4855
SPI Bus Interface
4/27
Table 3: Gain Control Settings
G2: Gain (dB)
G1: Gain (dB)
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
-34.5
-40.5
0
0
0
0
0
-33.0
-39.0
0
0
0
0
1
-31.5
-37.5
0
0
0
1
0
-30.0
-36.0
0
0
0
1
1
-28.5
-34.5
0
0
1
0
0
-27.0
-33.0
0
0
1
0
1
-25.5
-31.5
0
0
1
1
0
-24.0
-30.0
0
0
1
1
1
-22.5
-28.5
0
1
0
0
0
-21.0
-27.0
0
1
0
0
1
-19.5
-25.5
0
1
0
1
0
-18.0
-24.0
0
1
0
1
1
-16.5
-22.5
0
1
1
0
0
-15.0
-21.0
0
1
1
0
1
-13.5
-19.5
0
1
1
1
0
-12.0
-18.0
0
1
1
1
1
-10.5
-16.5
1
0
0
0
0
-9.0
-15.0
1
0
0
0
1
-7.5
-13.5
1
0
0
1
0
-6.0
-12.0
1
0
0
1
1
-4.5
-10.5
1
0
1
0
0
-3.0
-9.0
1
0
1
0
1
-1.5
-7.5
1
0
1
1
0
0.0
-6.0
1
0
1
1
1
1.5
-4.5
1
1
0
0
0
3.0
-3.0
1
1
0
0
1
4.5
-1.5
1
1
0
1
0
6.0
0.0
1
1
0
1
1
7.5
1.5
1
1
1
0
0
9.0
3.0
1
1
1
0
1
10.5
4.5
1
1
1
1
0
12.0
6.0
1
1
1
1
1
Absolute Maximum Ratings
TS4855
5/27
2.3 SPI Timing Diagram
3 ABSOLUTE MAXIMUM RATINGS
4 OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply voltage
1
1) All voltage values are measured with respect to the ground pin.
6
V
T
oper
Operating Free Air Temperature Range
-40 to + 85
C
T
stg
Storage Temperature
-65 to +150
C
T
j
Maximum Junction Temperature
150
C
R
thja
Flip Chip Thermal Resistance Junction to Ambient
2
2) Device is protected in case of over temperature by a thermal shutdown active @ 150C typ.
166
C/W
Pd
Power Dissipation
Internally Limited
ESD
Human Body Model
3
3) Human body model, 100pF discharged through a 1.5
k
resistor into pin of device.
2
kV
ESD
Machine Model
4
4) This is a minimum Value. Machine model ESD, a 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external
series resistor (internal resistor < 5
), into pin to pin of device.
5.) All PSRR data limits are guaranteed by evaluation tests.
100
V
Latch-up Immunity
200
mA
Lead Temperature (soldering, 10sec)
250
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
3 to 5
V
V
phin
Maximum Phone In Input Voltage
G
ND
to V
CC
V
V
Rin/
V
Lin
Maximum Rin & Lin Input Voltage
G
ND
to V
CC
V
T
SD
Thermal Shutdown Temperature
150
C
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