Features
Power monitoring and switching
for nonvolatile control of SRAMs
Write-protect control
Battery-low and battery-fail indi-
cators
Reset output for system power-on
reset
Input decoder for control of up to
2 banks of SRAM
3-volt primary cell input
3-volt rechargeable battery in-
put/output
General Description
The CMOS bq2203A SRAM Nonvolatile
Controller With Battery Monitor pro-
vides all the necessary functions for con-
verting one or two banks of standard
CMOS
SRAM
into
nonvolatile
read/write memory. The bq2203A is
compatible with the Personal Computer
Memory Card International Association
(PCMCIA) recommendations for
battery-backed static RAM memory
cards.
A precision comparator monitors the 5V
V
CC
input for an out-of-tolerance condi-
tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect
banks of SRAM.
Power for the external SRAMs is
switched from the V
CC
supply to the
battery-backup supply as V
CC
de-
cays. On a subsequent power-up, the
V
OUT
supply is automatically
switched from the backup supply to
the V
CC
supply. The external SRAMs
are write-protected until a power-
valid condition exists. The reset out-
put provides power-fail and power-on
resets for the system.
The battery
monitor indicates battery-low and
battery-fail conditions.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
1
1
PN220301.eps
16-Pin Narrow DIP or SOIC
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
BCS
CE
CECON1
CECON2
BCL
RST
NC
VOUT
BCP
NC
A
BCF
NC
THS
VSS
bq2203A
Nov. 1994 B
Pin Connections
Two banks of CMOS static RAM can be battery-backed us-
ing the V
OUT
and the conditioned chip-enable output pins
from the bq2203A. As the voltage input V
CC
slews down
during a power failure, the two conditioned chip-enable
outputs, CE
CON1
and CE
CON2
, are forced inactive
independent of the chip-enable input CE.
This activity unconditionally write-protects external SRAM
as V
CC
falls to an out-of-tolerance threshold V
PFD
. V
PFD
is
selected by the threshold select input pin, THS. If THS is
tied to V
SS
, the power-fail detection occurs at 4.62V typical
for 5% supply operation.
If THS is tied to V
CC
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to V
SS
or V
CC
for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t
WPT
(150
s maximum), the two chip-enable
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.
Functional Description
NV Controller With Battery Monitor
Pin Names
V
OUT
Supply output
RST
Reset output
THS
Threshold select input
CE
chip-enable active low input
CE
CON1
,
Conditioned chip-enable outputs
CE
CON2
A
Bank select input
BCF
Battery fail push-pull output
BCL
Battery low push-pull output
BC
P
3V backup supply input
BC
S
3V rechargeable backup supply input/output
NC
No connect
V
CC
5-volt supply input
V
SS
Ground
As the supply continues to fall past V
PFD
, an internal
switching device forces V
OUT
to the external backup en-
ergy source. CE
CON1
and CE
CON2
are held high by the
V
OUT
energy source.
During power-up, V
OUT
is switched back to the 5V sup-
ply as V
CC
rises above the backup cell input voltage
sourcing V
OUT
. Outputs CE
CON1
and CE
CON2
are held
inactive for time t
CER
(120ms maximum) after the
power supply has reached V
PFD
, independent of the CE
input, to allow for processor stabilization.
During power-valid operation, the CE input is passed
through to one of the two CE
CON
outputs with a propaga-
tion delay of less than 10ns. The CE input is output on
one of the two CE
CON
output pins depending on the level
of bank select input A, as shown in the Truth Table.
Bank select input A is usually tied to a high-order ad-
dress pin so that a large nonvolatile memory can be de-
signed using lower-density memory devices. Nonvolatil-
ity and decoding are achieved by hardware hookup as
shown in Figure 1.
The reset output (RST) goes active within t
PFD
(150
s
maximum) after V
PFD,
and remains active for a mini-
mum of 40ms (120ms maximum) after power returns
valid. The RST output can be used as the power-on re-
set for a microprocessor. Access to the external RAM
may begin when RST returns inactive.
Energy Cell Inputs--BC
P
, BC
S
Two backup energy source inputs are provided on the
bq2203A--a primary cell BC
P
and a secondary cell BC
S
.
The primary cell input is designed to accept any 3V pri-
mary battery (non-rechargeable), typically some type of
lithium chemistry. If a primary cell is not to be used, the
BC
P
pin should be tied to V
SS
. The secondary cell input
BC
S
is designed to accept constant-voltage current-
limited rechargeable cells.
During normal 5V power valid operation, 3.3V typical is out-
put on the BC
S
pin and is current-limited internally. Al-
though this charging method can be used with various 3V
secondary cells, it is specifically designed for a Panasonic VL
(vanadium-lithium) series of rechargeable cells.
2
FG220301.eps
CE
BCP
THS
VSS
VOUT
bq2203A
VCC
CE
CMOS
SRAM
VCC
5V
From Address
Decoder
CECON2
BCS
CECON1
A
RST
VCC
CE
CMOS
SRAM
To Microprocessor
3V Secondary
Cell
3V Primary
Cell
BCL
BCF
Figure 1. Hardware Hookup (5% Supply Operation)
Nov. 1994 B
bq2203A
If a secondary cell is not to be used, the BC
S
pin must be
tied directly to V
SS
.
V
CC
falling below V
PFD
starts the comparison of BC
S
and BC
P
. The BC input comparison continues until V
CC
rises above V
SO
. Power to V
OUT
begins with BC
S
and
switches to BC
P
only when BC
S
is less than BC
P
minus
V
BSO
. The controller alternates to the higher BC voltage
when the difference between the BC input voltages is
greater than V
BSO
. Alternating the backup batteries al-
lows one-at-a-time battery replacement and efficient use
of both backup batteries.
To prevent battery drain when there is no valid data to
retain, V
OUT
, CE
CON1
, and CE
CON2
are internally iso-
lated from BC
P
and BC
S
by either of two methods:
s
Initial connection of a battery to BC
P
or BC
S
(V
CC
grounded) or
s
Presentation of an isolation signal on CE.
A valid isolation signal requires CE low as V
CC
crosses
both V
PFD
and V
SO
during a power-down. See Figure
2.
Between these two points in time, CE must be
brought to V
CC
*(0.48 to 0.52) and held for at least 700ns.
The isolation signal is invalid if CE exceeds V
CC
*0.54 at
any point between V
CC
crossing V
PFD
and V
SO
.
The isolation function is terminated and the appropriate
battery is connected to V
OUT
, CE
CON1
, and CE
CON2
by
powering V
CC
up through V
PFD
.
Battery Monitor--BCL, BCF
As V
CC
rises past V
PFD
, the battery voltage on BC
P
is
compared with a dual-voltage reference. The result of
this comparison is latched internally, and output after
t
BC
when V
CC
rises past V
PFD
. If the battery voltage on
BC
P
is below V
BL
, then BCL is asserted low. If the bat-
tery is below V
BF
, then BCL and BCF are asserted low.
The results of this comparison remain latched until V
CC
falls below V
PFD
.
3
TD220101.eps
VCC
CE
VPFD
VSO
0.5 VCC
700ns
Figure 2. Battery Isolation Signal
Truth Table
Input
Output
CE
A
CE
CON1
CE
CON2
H
X
H
H
L
L
L
H
L
H
H
L
Nov. 1994 B
bq2203A
4
Recommended DC Operating Conditions
(TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
V
CC
Supply voltage
4.75
5.0
5.5
V
THS = V
SS
4.50
5.0
5.5
V
THS = V
CC
V
BCP
Backup cell input voltage
2.0
-
4.0
V
V
CC
< V
BC
V
BCS
2.0
-
4.0
V
V
CC
< V
BC
V
SS
Supply voltage
0
0
0
V
V
IL
Input low voltage
-0.3
-
0.8
V
V
IH
Input high voltage
2.2
-
V
CC
+ 0.3
V
THS
Threshold select
-0.3
-
V
CC
+ 0.3
V
Note:
Typical values indicate operation at T
A
= 25C, V
CC
= 5V.
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
V
CC
DC voltage applied on V
CC
relative to V
SS
-0.3 to +7.0
V
V
T
DC voltage applied on any pin excluding V
CC
relative to V
SS
-0.3 to +7.0
V
V
T
V
CC
+ 0.3
T
OPR
Operating temperature
0 to 70
C
Commercial
-40 to +85
C
"N" Industrial
T
STG
Storage temperature
-55 to +125
C
T
BIAS
Temperature under bias
-40 to +85
C
T
SOLDER
Soldering temperature
260
C
For 10 seconds
I
OUT
V
OUT
current
200
mA
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Nov. 1994 B
bq2203A
5
DC Electrical Characteristics
(TA = TOPR, VCC = 5V
10%)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
I
LI
Input leakage current
-
-
1
A
V
IN
= V
SS
to V
CC
V
OH
Output high voltage
2.4
-
-
V
I
OH
= -2.0mA
V
OHB
V
OH
, backup supply
V
BC
- 0.3
-
-
V
V
BC
> V
CC
, I
OH
= -10
A
V
OL
Output low voltage
-
-
0.4
V
I
OL
= 4.0mA
I
CC
Operating supply current
-
3
6
mA
No load on outputs
VPFD
Power-fail detect voltage
4.55
4.62
4.75
V
THS = V
SS
4.30
4.37
4.50
V
THS = V
CC
V
SO
Supply switch-over voltage
-
V
BC
-
V
ICCDR
Data-retention mode
current
-
-
100
nA
No load on outputs
VBC
Active backup cell voltage
-
V
BCS
-
V
V
BCS
> V
BCP
+ V
BSO
-
V
BCP
-
V
V
BCP
> V
BCS
+ V
BSO
V
BSO
Battery switch-over voltage
0.25
0.4
0.6
V
RBCS
BC
S
charge output internal
resistance
500
1000
1750
VBCSO
3.0V
VBCSO
BCS charge output voltage
3.15
3.3
3.5
V
V
CC
> V
PFD
, RST inactive,
full charge or no load
I
OUT1
V
OUT
current
-
-
160
mA
V
OUT
V
CC
- 0.3V
I
OUT2
V
OUT
current
-
100
-
A
V
OUT
V
BC
- 0.2V
V
BL
Voltage battery low
2.3
-
2.5
V
BC
P
input only
V
BF
Voltage battery fail
2.0
-
2.2
V
BC
P
input only
Note:
Typical values indicate operation at T
A
= 25C, V
CC
= 5V or V
BC
.
Capacitance
(TA = 25C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
C
IN
Input capacitance
-
-
8
pF
Input voltage = 0V
C
OUT
Output capacitance
-
-
10
pF
Output voltage = 0V
Note:
This parameter is sampled and not 100% tested.
Nov. 1994 B
bq2203A
bq2203A
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