Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ORDERING INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS
- PIN ASSIGNMENTS
- Terminal Functions
- FUNCTIONAL BLOCK DIAGRAM
- TYPICAL PERFORMANCE CURVES
- DIGITAL FILTER
- Digital Filter Response
- De-Emphasis Filter
- ANALOG DYNAMIC PERFORMANCE
- Supply Voltage Characteristics
- Temperature Characteristics
- SYSTEM CLOCK AND RESET FUNCTIONS
- System Clock Input
- Power-On and External Reset Functions
- AUDIO DATA INTERFACE
- Audio Serial Interface
- PCM Audio Data Formats and Timing
- (1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW
- (2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW
- (3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
- FUNCTION DESCRIPTIONS
- Audio data format
- Soft Mute
- De-Emphasis
- Zero Detect
- TYPICAL CONNECTION DIAGRAM
- APPLICATION INFORMATION
- APPLICATION CIRCUIT
- I/V Section
- Differential Section
- APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
- Application for Interfacing With an External Digital Filter
- System Clock (SCK) and Interface Timing
- Audio Format
- THEORY OF OPERATION
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
24 BIT, 192 kHz SAMPLING, ADVANCED SEGMENT,
AUDIO STEREO DIGITAL TO ANALOG CONVERTER
FEATURES
D
24-Bit Resolution
D
Analog Performance:
- Dynamic Range: 132 dB (9 V RMS, Mono)
129 dB (4.5 V RMS, Stereo)
127 dB (2 V RMS, Stereo)
- THD+N: 0.0004%
D
Differential Current Output: 7.8 mA p-p
D
8
Oversampling Digital Filter:
- Stop-Band Attenuation: 130 dB
- Pass-Band Ripple:
0.00001 dB
D
Sampling Frequency: 10 kHz to 200 kHz
D
System Clock: 128, 192, 256, 384, 512, or
768 f
S
With Autodetect
D
Accepts 16- and 24-Bit Audio Data
D
PCM Data Formats: Standard, I
2
S, and
Left-Justified
D
Optional Interface Available to External
Digital Filter or DSP
D
Digital De-Emphasis
D
Digital Filter Rolloff: Sharp or Slow
D
Soft Mute
D
Zero Flag
D
Dual-Supply Operation:
- 5-V Analog, 3.3-V Digital
D
5-V Tolerant Digital Inputs
D
Small 28-Lead SSOP Package, Lead-Free
Product
APPLICATIONS
D
A/V Receivers
D
DVD Players
D
Musical Instruments
D
HDTV Receivers
D
Car Audio Systems
D
Digital Multitrack Recorders
D
Other Applications Requiring 24-Bit Audio
DESCRIPTION
The PCM1794 is a monolithic CMOS integrated circuit that
includes stereo digital-to-analog converters and support
circuitry in a small 28-lead SSOP package. The data
converters use TI's advanced segment DAC architecture
to achieve excellent dynamic performance and improved
tolerance to clock jitter. The PCM1794 provides balanced
current outputs, allowing the user to optimize analog
performance externally. Sampling rates up to 200 kHz are
supported.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Burr Brown Products
from Texas Instruments
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
2
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PCM1794DB
28-lead SSOP
28DB
25
C to 85
C
PCM1794
PCM1794DB
Tube
PCM1794DB
28-lead SSOP
28DB
25
C to 85
C
PCM1794
PCM1794DBR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PCM1794
Supply voltage
VCC1, VCC2L, VCC2R
0.3 V to 6.5 V
Supply voltage
VDD
0.3 V to 4 V
Supply voltage differences: VCC1, VCC2L, VCC2R
0.1 V
Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND
0.1 V
Digital input voltage
LRCK, DATA, BCK, SCK, FMT1, FMT0, MONO, CHSL, DEM, MUTE, RST,
0.3 V to 6.5 V
Digital input voltage
ZERO
0.3 V to (VDD + 0.3 V) < 4 V
Analog input voltage
0.3 V to (VCC + 0.3 V) < 6.5 V
Input current (any pins except supplies)
10 mA
Ambient temperature under bias
40
C to 125
C
Storage temperature
55
C to 150
C
Junction temperature
150
C
Lead temperature (soldering)
260
C, 5 s
Package temperature (IR reflow, peak)
250
C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25
C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless
otherwise noted
PARAMETER
TEST CONDITIONS
PCM1794DB
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
24
Bits
DATA FORMAT
Audio data interface format
Standard, I2S, left justified
Audio data bit length
16-, 24-bit selectable
Audio data format
MSB first, 2s complement
fS
Sampling frequency
10
200
kHz
System clock frequency
128, 192, 256, 384, 512, 768 fS
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
VIH
Input logic level
2
VDC
VIL
Input logic level
0.8
VDC
IIH
Input logic current
VIN = VDD
10
A
IIL
Input logic current
VIN = 0 V
10
A
VOH
Output logic level
IOH = 2 mA
2.4
VDC
VOL
Output logic level
IOL = 2 mA
0.4
VDC
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
3
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25
C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless
otherwise noted
PARAMETER
TEST CONDITIONS
PCM1794DB
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE (2-V RMS OUTPUT) (1)(2)
fS = 44.1 kHz
0.0004%
0.0008%
THD+N at VOUT = 0 dB
fS = 96 kHz
0.0008%
THD+N at VOUT = 0 dB
fS = 192 kHz
0.0015%
EIAJ, A-weighted, fS = 44.1 kHz
123
127
Dynamic range
EIAJ, A-weighted, fS = 96 kHz
127
dB
Dynamic range
EIAJ, A-weighted, fS = 192 kHz
127
dB
EIAJ, A-weighted, fS = 44.1 kHz
123
127
Signal-to-noise ratio
EIAJ, A-weighted, fS = 96 kHz
127
dB
Signal-to-noise ratio
EIAJ, A-weighted, fS = 192 kHz
127
dB
fS = 44.1 kHz
120
123
Channel separation
fS = 96 kHz
122
dB
Channel separation
fS = 192 kHz
120
dB
Level linearity error
VOUT = 120 dB
1
dB
DYNAMIC PERFORMANCE (4.5-V RMS Output) (1)(3)
fS = 44.1 kHz
0.0004%
THD+N at VOUT = 0 dB
fS = 96 kHz
0.0008%
THD+N at VOUT = 0 dB
fS = 192 kHz
0.0015%
EIAJ, A-weighted, fS = 44.1 kHz
129
Dynamic range
EIAJ, A-weighted, fS = 96 kHz
129
dB
Dynamic range
EIAJ, A-weighted, fS = 192 kHz
129
dB
EIAJ, A-weighted, fS = 44.1 kHz
129
Signal-to-noise ratio
EIAJ, A-weighted, fS = 96 kHz
129
dB
Signal-to-noise ratio
EIAJ, A-weighted, fS = 192 kHz
129
dB
fS = 44.1 kHz
124
Channel separation
fS = 96 kHz
123
dB
Channel separation
fS = 192 kHz
121
dB
DYNAMIC PERFORMANCE (MONO MODE) (1)(3)
fS = 44.1 kHz
0.0004%
THD+N at VOUT = 0 dB
fS = 96 kHz
0.0008%
THD+N at VOUT = 0 dB
fS = 192 kHz
0.0015%
EIAJ, A-weighted, fS = 44.1 kHz
132
Dynamic range
EIAJ, A-weighted, fS = 96 kHz
132
dB
Dynamic range
EIAJ, A-weighted, fS = 192 kHz
132
dB
EIAJ, A-weighted, fS = 44.1 kHz
132
Signal-to-noise ratio
EIAJ, A-weighted, fS = 96 kHz
132
dB
Signal-to-noise ratio
EIAJ, A-weighted, fS = 192 kHz
132
dB
(1) Filter condition:
THD+N: 20-Hz HPF, 20-kHz apogee LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two
t
Cascade audio measurement system by Audio Precision
in the
averaging mode.
(2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 24.
(3) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 25.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
4
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25
C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless
otherwise noted
PARAMETER
TEST CONDITIONS
PCM1794DB
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
Gain error
6
2
6
% of FSR
Gain mismatch, channel-to-channel
3
0.5
3
% of FSR
Bipolar zero error
At BPZ
2
0.5
2
% of FSR
Output current
Full scale (0 dB)
7.8
mA p-p
Center current
At BPZ
6.2
mA
DIGITAL FILTER PERFORMANCE
De-emphasis error
0.004
dB
FILTER CHARACTERISTICS-1: SHARP ROLLOFF
Pass band
0.00001 dB
0.454 fS
Pass band
3 dB
0.49 fS
Stop band
0.546 fS
Pass-band ripple
0.00001
dB
Stop-band attenuation
Stop band = 0.546 fS
130
dB
Delay time
55/fS
s
FILTER CHARACTERISTICS-2: SLOW ROLLOFF
Pass band
0.04 dB
0.254 fS
Pass band
3 dB
0.46 fS
Stop band
0.732 fS
Pass-band ripple
0.001
dB
Stop-band attenuation
Stop band = 0.732 fS
100
dB
Delay time
18/fS
s
POWER SUPPLY REQUIREMENTS
VDD
3
3.3
3.6
VDC
VCC1
Voltage range
VCC2L
Voltage range
4.75
5
5.25
VDC
VCC2R
4.75
5
5.25
VDC
(1)
fS = 44.1 kHz
12
15
IDD
(1)
fS = 96 kHz
23
mA
IDD
Supply current (1)
fS = 192 kHz
45
mA
Supply current (1)
fS = 44.1 kHz
33
40
ICC
fS = 96 kHz
35
mA
ICC
fS = 192 kHz
37
mA
(1)
fS = 44.1 kHz
205
250
Power dissipation (1)
fS = 96 kHz
250
mW
Power dissipation (1)
fS = 192 kHz
335
mW
TEMPERATURE RANGE
Operation temperature
25
85
C
JA
Thermal resistance
28-pin SSOP
100
C/W
(1) Input is BPZ data.
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
5
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MONO
CHSL
DEM
LRCK
DATA
BCK
SCK
DGND
V
DD
MUTE
FMT0
FMT1
ZERO
RST
V
CC
2L
AGND3L
I
OUT
L
I
OUT
L+
AGND2
V
CC
1
V
COM
L
V
COM
R
I
REF
AGND1
I
OUT
R
I
OUT
R+
AGND3R
V
CC
2R
PCM1794
(TOP VIEW)
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
6
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
PIN
I/O
DESCRIPTIONS
AGND1
19
Analog ground (internal bias)
AGND2
24
Analog ground (internal bias)
AGND3L
27
Analog ground (L-channel DACFF)
AGND3R
16
Analog ground (R-channel DACFF)
BCK
6
I
Bit clock input (1)
CHSL
2
I
L-, R-channel select (1)
DATA
5
I
Serial audio data input (1)
DEM
3
I
De-emphasis enable (1)
DGND
8
Digital ground
FMT0
11
I
Audio data format select (1)
FMT1
12
I
Audio data format select (1)
IOUTL+
25
O
L-channel analog current output +
IOUTL
26
O
L-channel analog current output
IOUTR+
17
O
R-channel analog current output +
IOUTR
18
O
R-channel analog current output
IREF
20
Output current reference bias pin
LRCK
4
I
Left and right clock (fS) input (1)
MONO
1
I
Monaural mode enable (1)
MUTE
10
I
Mute control (1)
RST
14
I
Reset(1)
SCK
7
I
System clock input(1)
VCC1
23
Analog power supply, 5 V
VCC2L
28
Analog power supply (L-channel DACFF), 5 V
VCC2R
15
Analog power supply (R-cahnnel DACFF), 5 V
VCOML
22
L-channel internal bias decoupling pin
VCOMR
21
R-channel internal bias decoupling pin
VDD
9
Digital power supply, 3.3 V
ZERO
13
O
Zero flag
(1) Schmitt-trigger input, 5-V tolerant
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
7
FUNCTIONAL BLOCK DIAGRAM
Power Supply
FMT1
SCK
Advanced
Segment
DAC
Modulator
Bias
and
Vref
AGND2
V
DD
V
CC
1
V
CC
2L
V
CC
2R
AGND1
8
Oversampling
Digital
Filter
and
Function
Control
Audio
Data Input
I/F
LRCK
BCK
DATA
DEM
RST
AGND3L
AGND3R
DGND
Current
Segment
DAC
IREF
Function
Control
I/F
Zero
Detect
ZERO
System
Clock
Manager
FMT0
MUTE
Current
Segment
DAC
MONO
CHSL
VCOML
VCOMR
IOUTL+
IOUTL
I/V and Filter
VOUTL
IOUTR+
IOUTR
I/V and Filter
VOUTR
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
8
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter Response
Figure 1. Frequency Response, Sharp Rolloff
Frequency [
fS]
-200
-150
-100
-50
0
0
1
2
3
4
Amplitude dB
AMPLITUDE
vs
FREQUENCY
Figure 2. Pass-Band Ripple, Sharp Rolloff
Frequency [
fS]
-2
-1
0
1
2
0.0
0.1
0.2
0.3
0.4
0.5
Amplitude dB
AMPLITUDE
vs
FREQUENCY
0.00002
0
0.00001
0.00002
0.00001
Figure 3. Frequency Response, Slow Rolloff
Frequency [
fS]
-200
-150
-100
-50
0
0
1
2
3
4
Amplitude dB
AMPLITUDE
vs
FREQUENCY
Figure 4. Transition Characteristics, Slow Rolloff
Frequency [
fS]
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Amplitude dB
AMPLITUDE
vs
FREQUENCY
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
9
De-Emphasis Filter
Figure 5
f Frequency kHz
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
16
18
20
De-emphasis Level dB
DE-EMPHASIS LEVEL
vs
FREQUENCY
fS = 44.1 kHz
Figure 6
f Frequency kHz
-20
-15
-10
-5
0
5
10
15
20
0
2
4
6
8
10
12
14
16
18
20
DE-EMPHASIS ERROR
vs
FREQUENCY
0.020
0
0.015
0.020
0.015
0.010
0.005
0.010
0.005
De-emphasis Error dB
fS = 44.1 kHz
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
10
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
Figure 7
4.50
4.75
5.00
5.25
5.50
VCC Supply Voltage V
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
0.01
0.001
0.0001
fS = 192 kHz
fS = 96 kHz
THD+N T
otal Harmonic Distortion + Noise %
fS = 48 kHz
Figure 8
VCC Supply Voltage V
122
124
126
128
130
132
4.50
4.75
5.00
5.25
5.50
Dynamic Range dB
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
fS = 96 kHz
fS = 48 kHz
fS = 192 kHz
Figure 9
VCC Supply Voltage V
122
124
126
128
130
132
4.50
4.75
5.00
5.25
5.50
SNR Signal-to-Noise Ratio dB
SIGNAL-to-NOISE RATIO
vs
SUPPLY VOLTAGE
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
Figure 10
VCC Supply Voltage V
120
122
124
126
128
130
4.50
4.75
5.00
5.25
5.50
Channel Separation dB
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
NOTE: TA = 25
C, VDD = 3.3 V, measurement circuit is Figure 25 (VOUT = 4.5 V rms).
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
11
Temperature Characteristics
Figure 11
-50
-25
0
25
50
75
100
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
0.01
0.001
0.0001
fS = 192 kHz
fS = 96 kHz
THD+N T
otal Harmonic Distortion + Noise %
fS = 48 kHz
TA Free-Air Temperature
C
Figure 12
TA Free-Air Temperature
C
122
124
126
128
130
132
-50
-25
0
25
50
75
100
Dynamic Range dB
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
fS = 192 kHz
fS = 96 kHz
fS = 48 kHz
Figure 13
TA Free-Air Temperature
C
122
124
126
128
130
132
-50
-25
0
25
50
75
100
SNR Signal-to-Noise Ratio dB
SIGNAL-to-NOISE RATIO
vs
FREE-AIR TEMPERATURE
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
Figure 14
TA Free-Air Temperature
C
120
122
124
126
128
130
-50
-25
0
25
50
75
100
Channel Separation dB
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
fS = 192 kHz
fS = 48 kHz
fS = 96 kHz
NOTE: VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 25 (VOUT = 4.5 V rms).
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
12
NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25
C, VDD = 3.3 V,
VCC = 5 V, measurement circuit is Figure 25.
Figure 15. 60-db Output Spectrum, BW = 20 kHz
f Frequency kHz
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
0
2
4
6
8
10
12
14
16
18
20
Amplitude dB
AMPLITUDE
vs
FREQUENCY
NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25
C, VDD = 3.3 V,
VCC = 5 V, measurement circuit is Figure 25.
Figure 16. 60-db Output Spectrum, BW = 100 kHz
f Frequency kHz
-160
-140
-120
-100
-80
-60
-40
-20
0
0
10
20
30
40
50
60
70
80
90
100
Amplitude dB
AMPLITUDE
vs
FREQUENCY
NOTE: fS = 48 kHz, TA = 25
C, VDD = 3.3 V, VCC = 5 V,
measurement circuit is Figure 25.
Figure 17. THD+N vs Input Level
-100
-80
-60
-40
-20
0
Input Level dBFS
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
10
0.1
0.01
0.001
0.0001
THD+N T
otal Harmonic Distortion + Noise %
1
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
13
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1794 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1794 has a system clock detection circuit
that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system
clock frequencies for common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators
is an excellent choice for providing the PCM1794 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (FSCK) (MHz)
SAMPLING FREQUENCY
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
32 kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1 kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
49.152
73.728
192 kHz
24.576
36.864
49.152
73.728
(1)
(1)
(1) This system clock rate is not supported for the given sampling frequency.
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2.0 V
0.8 V
H
L
PARAMETERS
MIN
MAX
UNITS
t(SCY)
System clock pulse cycle time
13
ns
t(SCKH) System clock pulse duration, HIGH
0.4 t(SCY)
ns
t(SCKL) System clock pulse duration, LOW
0.4 t(SCY)
ns
Figure 18. System Clock Input Timing
Power-On and External Reset Functions
The PCM1794 includes a power-on reset function. Figure 19 shows the operation of this function. With V
DD
> 2 V,
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
V
DD
> 2 V.
The PCM1794 also includes an external reset capability using the RST input (pin 14). This allows an external
controller or master reset circuit to force the PCM1794 to initialize to its default reset state.
Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock
periods. The external reset is especially useful in applications where there is a delay between the PCM1794 power
up and system clock activation.
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
14
Reset
Reset Removal
1024 System Clocks
VDD
2.4 V (Max)
2.0 V (Typ)
1.6 V (Min)
Internal Reset
System Clock
Figure 19. Power-On Reset Timing
Reset
Reset Removal
1024 System Clocks
Internal Reset
System Clock
RST (Pin 14)
t(RST)
50 % of VDD
PARAMETERS
MIN
MAX
UNITS
t(RST)
Reset pulse duration, LOW
20
ns
Figure 20. External Reset Timing
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
15
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio
interface. Serial data is clocked into the PCM1794 on the rising edge of BCK. LRCK is the serial audio left/right word
clock.
The PCM1794 requires the synchronization of LRCK and the system clock, but does not need a specific phase
relation between LRCK and the system clock.
If the relationship between LRCK and the system clock changes more than
6 BCK, internal operation is initialized
within 1/f
S
and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the
system clock is completed.
PCM Audio Data Formats and Timing
The PCM1794 supports industry-standard audio data formats, including standard right-justified, I
2
S, and
left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits,
FMT1 (pin 12), and FMT0 (pin 11) as shown in Table 2. All formats require binary twos-complement, MSB-first audio
data. Figure 21 shows a detailed timing diagram for the serial audio interface.
DATA
t(BCH)
50% of VDD
BCK
LRCK
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
50% of VDD
50% of VDD
t(BL)
PARAMETERS
MIN
MAX
UNITS
t(BCY)
BCK pulse cycle time
70
ns
t(BCL)
BCK pulse duration, LOW
30
ns
t(BCH)
BCK pulse duration, HIGH
30
ns
t(BL)
BCK rising edge to LRCK edge
10
ns
t(LB)
LRCK edge to BCK rising edge
10
ns
t(DS)
DATA setup time
10
ns
t(DH)
DATA hold time
10
ns
--
LRCK clock duty
50%
2 bit clocks
Figure 21. Timing of Audio Interface
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
16
14 15 16
1
2
15 16
MSB
LSB
1
2
15 16
22 23 24
LSB
1
23
2
24
1
23
2
24
2
1
MSB
LSB
1
2
24
1
2
24
LSB
1
2
24
2
1
1
2
24
BCK
L-Channel
DATA
R-Channel
1/fS
DATA
LRCK
Audio Data Word = 16-Bit
Audio Data Word = 24-Bit
BCK
L-Channel
DATA
R-Channel
1/fS
LRCK
Audio Data Word = 24-Bit
23
23
23
23
BCK
L-Channel
DATA
R-Channel
1/fS
LRCK
Audio Data Word = 24-Bit
MSB
MSB
(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW
(1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW
(3) I
2
S Data Format; L-Channel = LOW, R-Channel = HIGH
Figure 22. Audio Data Input Formats
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
17
FUNCTION DESCRIPTIONS
Audio data format
Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1794 also supports monaural mode and DF
bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1794 can select the DF rolloff characteristics.
Table 2. Audio Data Format Select
MONO
CHSL
FMT1
FMT0
FORMAT
STEREO/MONO
DF ROLLOFF
0
0
0
0
I2S
Stereo
Sharp
0
0
0
1
Left-justified format
Stereo
Sharp
0
0
1
0
Standard, 16-bit
Stereo
Sharp
0
0
1
1
Standard, 24-bit
Stereo
Sharp
0
1
0
0
I2S
Stereo
Slow
0
1
0
1
Left-justified format
Stereo
Slow
0
1
1
0
Standard, 16-bit
Stereo
Slow
0
1
1
1
Digital filter bypass
Mono
1
0
0
0
I2S
Mono, L-channel
Sharp
1
0
0
1
Left-justified format
Mono, L-channel
Sharp
1
0
1
0
Standard, 16-bit
Mono, L-channel
Sharp
1
0
1
1
Standard, 24-bit
Mono, L-channel
Sharp
1
1
0
0
I2S
Mono, R-channel
Sharp
1
1
0
1
Left-justified format
Mono, R-channel
Sharp
1
1
1
0
Standard, 16-bit
Mono, R-channel
Sharp
1
1
1
1
Standard, 24-bit
Mono, R-channel
Sharp
Soft Mute
The PCM1794 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned
to the bipolar zero level in 0.5-dB steps with a transition speed of 1/f
S
per step. This system provides pop-free muting
of the DAC output.
De-Emphasis
The PCM1794 has a de-emphasis filters for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled
using DEM (pin 3).
Zero Detect
When the PCM1794 detects that the audio input data in the L-channel and the R-channel is continuously zero for
1024 f
S
, the PCM1794 sets ZERO (pin 13)to HIGH.
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
18
TYPICAL CONNECTION DIAGRAM
DATA
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
PCM1794
BCK
SCK
DGND
VDD
MUTE
FMT0
FMT1
ZERO
RST
AGND2
IOUTR
VCC1
VCOML
VCOMR
IREF
IOUTR+
AGND3R
AGND1
+
MONO
1
2
3
4
CHSL
DEM
LRCK
28
27
26
25
VCC2L
AGND3L
IOUTL
IOUTL+
Controller
VOUT
L-Channel
5 V
VCC2R
0.1
F
Controller
10
F
3.3 V
PCM
Audio Data
Source
0.1
F
10
F
Cf
Rf
Differential
to
Single
Converter
With
Low-Pass
Filter
+
+
47
F
47
F
5 V
10
F
10 k
+
Cf
Rf
+
VOUT
R-Channel
Cf
Rf
Differential
to
Single
Converter
With
Low-Pass
Filter
+
Cf
Rf
0.1
F
10
F
5 V
+
+
+
+
Figure 23. Typical Application Circuit
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
19
APPLICATION INFORMATION
APPLICATION CIRCUIT
The design of the application circuit is very important in order to actually realize the high S/N ratio of which the
PCM1794 is capable. This is because noise and distortion that are generated in an application circuit are not
negligible.
In the circuit of Figure 24, the output level is 2 V RMS, and 127 dB S/N is achieved. The circuit of Figure 25 can realize
the highest performance. In this case the output level is set to 4.5 V RMS and 129 dB S/N is achieved (stereo mode).
In monaural mode, if the output of the L-channel and R-channel is used as a balanced output, 132 dB S/N is achieved
(see Figure 26).
I/V Section
The current of the PCM1794 on each of the output pins (I
OUT
L+, I
OUT
L, I
OUT
R+, I
OUT
R) is 7.8 mA p-p at 0 dB (full
scale). The voltage output level of the I/V converter (Vi) is given by following equation:
Vi = 7.8 mA pp
R
f
(R
f
: feedback resistance of I/V converter)
An NE5534 op amp is recommended for the I/V circuit to obtain the specified performance. Dynamic performance
such as the gain bandwidth, settling time, and slew rate of the op amp affects the audio dynamic performance of the
I/V section.
Differential Section
The PCM1794 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each
channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter
function.
The op amp recommended for the differential circuit is the Linear Technology LT1028, because its input noise is low.
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
20
+
R1
750
2
3
7
5
8
6
4
C11
0.1
F
C17
22 pF
VCC
C1
2200 pF
C12
0.1
F
VEE
U1
NE5534
IOUT
+
R2
750
2
3
7
5
8
6
4
C13
0.1
F
C18
22 pF
VCC
C2
2200 pF
C14
0.1
F
VEE
U2
NE5534
IOUT+
+
2
3
7
5
6
4
C15
0.1
F
C19
33 pF
VCC
C16
0.1
F
VEE
U3
LT1028
R7
100
C3
2700 pF
R5
270
C4
2700 pF
R6
270
R3
560
R4
560
VCC = 15 V
VEE = 15 V
fC = 217 kHz
Figure 24. Measurement Circuit, V
OUT
= 2 V RMS
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
21
+
R1
820
2
3
7
5
8
6
4
C11
0.1
F
C17
22 pF
VCC
C1
2200 pF
C12
0.1
F
VEE
U1
NE5534
IOUT
+
R2
820
2
3
7
5
8
6
4
C13
0.1
F
C18
22 pF
VCC
C2
2200 pF
C14
0.1
F
VEE
U2
NE5534
IOUT+
+
2
3
7
5
6
4
C15
0.1
F
C19
33 pF
VCC
C16
0.1
F
VEE
U3
LT1028
R7
100
C3
2700 pF
R5
360
C4
2700 pF
R6
360
R3
360
R4
360
VCC = 15 V
VEE = 15 V
fC = 162 kHz
Figure 25. Measurement Circuit, V
OUT
= 4.5 V RMS
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
22
IOUT
Figure 25
Circuit
IOUT+
IOUTL (Pin 26)
IOUTL+ (Pin 25)
OUT+
1
2
3
Balanced Out
IOUT
Figure 25
Circuit
IOUT+
IOUTR (Pin 18)
IOUTR+ (Pin 17)
OUT
Figure 26. Measurement Circuit for Monaural Mode
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DATA
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
PCM1794
BCK
SCK
DGND
VDD
MUTE
FMT0
FMT1
ZERO
RST
AGND2
IOUTR
VCC1
VCOML
VCOMR
IREF
IOUTR+
AGND3R
AGND1
MONO
1
2
3
4
CHSL
DEM
LRCK
28
27
26
25
VCC2L
AGND3L
IOUTL
IOUTL+
VCC2R
DATA
Analog
Output Stage
(See Figure 23)
WDCK
BCK
SCK
External
Filter
Device
VDD
Figure 27. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
23
Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter
to perform the interpolation function. The following pin settings enable the external digital filter application mode.
D
MONO (pin 1) = LOW
D
CHSL (Pin 2) = HIGH
D
FMT0 (Pin 11) = HIGH
D
FMT1 (pin 12) = HIGH
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 27. The word clock (WDCK) must be operated at 8
or 4
the desired sampling frequency, f
S
.
System Clock (SCK) and Interface Timing
The PCM1794 in an application using an external digital filter requires the synchronization of WDCK and the system
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, and DATA is
shown in Figure 29.
Audio Format
The PCM1794 in the external digital filter interface mode supports right-justified audio formats including 24-bit audio
data, as shown in Figure 28.
BCK
1/4 fS or 1/8 fS
WDCK
Audio Data Word = 24-Bit
MSB
LSB
16
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
24
23
20
17 18 19
24
21 22 23
DATA
Figure 28. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
24
DATA
t(BCH)
50% of VDD
BCK
WDCK
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
50% of VDD
50% of VDD
t(BL)
PARAMETER
MIN
MAX
UNITS
t(BCY) BCK pulse cycle time
20
ns
t(BCL) BCK pulse duration, LOW
7
ns
t(BCH) BCK pulse duration, HIGH
7
ns
t(BL)
BCK rising edge to WDCK falling edge
5
ns
t(LB)
WDCK falling edge to BCK rising edge
5
ns
t(DS)
DATA setup time
5
ns
t(DH)
DATA hold time
5
ns
Figure 29. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
THEORY OF OPERATION
Analog Output
Digital Input
24 Bits
8 fS
MSB
and
Lower 18 Bits
Upper
6 Bits
ICOB
Decoder
3rd-Order
5-Level
Sigma-Delta
Advanced
DWA
Current
Segment
DAC
04
Level
062
Level
066
Figure 30. Advanced Segment DAC
The PCM1794 uses TI's advanced segment DAC architecture to achieve excellent dynamic performance and
improved tolerance to clock jitter. The PCM1794 provides balanced current outputs.
Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted
to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed
by a five-level third-order delta-sigma modulator operated at 64 f
S
by default. The 1 level of the modulator is equivalent
to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order
delta-sigma modulator are summed together to create an up-to-66-level digital code, and then processed by
data-weighted averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from
the DWA is converted to an analog output in the differential-current segment section.
This architecture has overcome the various drawbacks of conventional multibit processing and also achieves
excellent dynamic performance.
PCM1794
SLES080B MAY 2003 REVISED NOVEMBER 2003
www.ti.com
25
Analog output
The following table and Figure 31 show the relationship between the digital input code and analog output.
800000 (FS)
000000 (BPZ)
7FFFFF (+FS)
IOUTN [mA]
2.3
6.2
10.1
IOUTP [mA]
10.1
6.2
2.3
VOUTN [V]
1.725
4.65
7.575
VOUTP [V]
7.575
4.65
1.725
VOUT [V]
2.821
0
2.821
NOTE: VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the
measurement circuit of Figure 24.
-12
-10
-8
-6
-4
-2
0
Input Code Hex
IOUTN
I O
Output Current mA
OUTPUT CURRENT
vs
INPUT CODE
800000(FS)
000000(BPZ)
7FFFFF(+FS)
IOUTP
Figure 31. The Relationship Between Digital Input and Analog Output
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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