SN74AS1843
9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SDAS127 APRIL 1987
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1
Copyright
1987, Texas Instruments Incorporated
PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of Texas Instruments standard
warranty. Production processing does not
necessarily include testing of all parameters.
Center V
CC
and GND Configuration
Provides Minimum Lead Inductance in High
Current Switching Applications
3-State Buffer-Type Outputs Drive
Bus-Lines Directly
Bus-Structured Pinout
Provide Extra Bus Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
Buffered Control Inputs to Reduce DC
Loading
Power-Up High Impedance
Package Options Include Plastic DIPs. Use
the
AS843 for Plastic and Ceramic Chip
Carriers and "Small Outline" Package
Options
Dependable Texas Instruments Quality and
Reliability
description
This 9-bit latch device features three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The nine latches are transparent D-type and have
noninverting data (D) inputs.
A buffered output control (OC) input can be used
to place the nine outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pullup components.
The output control (OC) does not affect the
internal operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are off.
The SN74AS1843 is characterized for operation
from 0
C to 70
C.
NT Package
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5Q
4Q
3Q
2Q
1Q
VCC
OC
1D
2D
3D
4D
5D
6Q
7Q
8Q
9Q
PRE
C
GND
CLR
9D
8D
7D
6D
PRE
CLR
OC
C
D
Q
L
X
L
X
X
H
H
L
L
X
X
L
H
H
L
H
L
L
H
H
L
H
H
H
H
H
L
L
X
QO
X
X
H
X
X
Z
INPUTS
OUTPUT
FUNCTION TABLE
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12,
7
20
17
19
8
9
10
11
12
13
14
15
5
4
3
2
1
24
23
22
EN
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
C1
R
S2
OC
PRE
CLR
C
1D
2D
3D
4D
5D
6D
7D
8D
16
21
9Q
9D
2
SN74AS1843
9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SDAS127 APRIL 1987
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
S
C1
1D
R
1D
8
1Q
5
S
C1
1D
R
2D
9
2Q
4
S
C1
1D
R
3D
10
3Q
3
S
C1
1D
R
4D
11
4Q
2
S
C1
1D
R
5D
12
5Q
1
S
C1
1D
R
6D
13
6Q
24
S
C1
1D
R
7D
14
7Q
23
S
C1
1D
R
8D
15
8Q
22
S
C1
1D
R
9D
16
9Q
21
C
19
CLR
17
PRE
20
OC
7
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
tw
Pulse duration, enable C high
ns
tr
Recovery time
ns
VOL
V
SN74AS1843
9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SDAS127 APRIL 1987
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
24
mA
IOL
Low-level output current
48
mA
CLR or PRE low
4
C high
4
tsu
Setup time, data before enable C
2.5
ns
th
Hold time, data after enable C
2.5
ns
PRE
15
CLR
14
TA
Operating free-air temperature
0
70
C
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
V
VCC = 4.5 V,
IOH = 2 mA
VCC 2
VOH
VCC = 4.5 V,
IOH = 15 mA
2.4
3.2
V
VCC = 4.5 V,
IOH = 24 mA
2
VCC = 4.5 V,
IOL = 32 mA
VCC = 4.5 V,
IOL = 48 mA
0.35
0.5
IOZH
VCC = 5.5 V,
VO = 2.7 V
50
A
IOZL
VCC = 5.5 V,
VO = 0.4 V
50
A
II
VCC = 5.5 V,
VI = 7 V
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
A
IIL
VCC = 5.5 V,
VI = 0.4 V
.05
mA
IO
VCC = 5.5 V,
VO = 2.25 V
30
112
mA
Output high
37
62
ICC
VCC = 5.5 V,
Output low
56
92
mA
Outputs disabled
56
92
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
ns
ns
ns
ns
D
C
OC
OC
Q
Q
Q
Q
SN74AS1843
9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SDAS127 APRIL 1987
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and free-air temperature
(see Note 2)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500
,
R2 = 500
,
TA = MIN to MAX
MIN
MAX
tPLH
1
6.5
tPHL
1
9
tPLH
2
12
tPHL
2
12
tPLH
PRE
Q
2
10
ns
tPHL
CLR
Q
2
13
ns
tPZH
2
10.5
tPZL
2
13.5
tPHZ
1
8
tPLZ
1
8
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the
ALS/AS Logic Data Book, 1986.
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Copyright
1998, Texas Instruments Incorporated
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