DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
LE
SN74BCT29844
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS077A SEPTEMBER 1991 REVISED NOVEMBER 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29844 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing wider buffer registers,
I/O ports, bidirectional bus drivers with parity, and
working registers.
The nine latches are transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs are
complementary to the inverting data (D) inputs.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pull-up components.
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74BCT29844 is characterized for operation from 0
C to 70
C.
FUNCTION TABLE
INPUTS
OUTPUT
PRE
CLR
OE
LE
D
Q
L
X
L
X
X
H
H
L
L
X
X
L
H
H
L
H
L
H
H
H
L
H
H
L
H
H
L
L
X
Q0
X
X
H
X
X
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74BCT29844
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS077A SEPTEMBER 1991 REVISED NOVEMBER 1993
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
logic diagram (positive logic)
OE
1D
2
3
4
5
6
S2
14
1Q
23
2Q
22
3Q
21
4Q
20
5Q
19
6Q
18
7Q
17
8Q
16
9Q
15
7
8
9
10
EN
1
OE
LE
1D
1Q
1
13
2
23
To Eight Other Channels
C1
13
LE
R
11
PRE
CLR
PRE
14
CLR
11
S
C1
1D
R
1D
2D
3D
4D
5D
6D
7D
8D
9D
2
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, V
O
0.5 V to 7 V
. . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
18
mA
IOH
High-level output current
24
mA
IOL
Low-level output current
48
mA
TA
Operating free-air temperature
0
70
C
SN74BCT29844
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS077A SEPTEMBER 1991 REVISED NOVEMBER 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
V
VOH
VCC = 4 5 V
IOH = 15 mA
2.4
V
VOH
VCC = 4.5 V
IOH = 24 mA
2
V
VOL
VCC = 4.75 V,
IOH = 3 mA
2.7
V
VOL
VCC = 4.5 V,
IOL = 48 mA
0.42
0.55
V
II
VCC = 5.5 V,
VI = 7 V
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
10
75
A
IIL
VCC = 5.5 V,
VI = 0.5 V
0.2
mA
IOS
VCC = 5.5 V,
VO = 0
75
275
mA
IOZH
VCC = 5.5 V,
VO = 2.7 V
20
A
IOZL
VCC = 5.5 V,
VO = 0.5 V
20
A
ICCL
VCC = 5.5 V,
Outputs open
3
7
mA
ICCH
VCC = 5.5 V,
Outputs open
24
35
mA
ICCZ
VCC = 5.5 V,
Outputs open
3
7
mA
Ci
VCC = 5 V,
VI = 2.5 V or 0.5 V
5
pF
Co
VCC = 5 V,
VO = 2.5 V or 0.5 V
8
pF
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
PRE low
4
4
tw
Pulse duration
CLR low
4
4
ns
LE high
4
4
t
Setup time data before LE
High or low
2.5
2.5
ns
tsu
Setup time, data before LE
PRE or CLR inactive
2
2
ns
th
Hold time data after LE
High
2
2
ns
th
Hold time, data after LE
Low
3
3
ns
SN74BCT29844
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS077A SEPTEMBER 1991 REVISED NOVEMBER 1993
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Note 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
MIN
MAX
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
tPLH
D
Q
1.8
5
7.3
1.8
9
ns
tPHL
D
Q
2.2
5
7
2.2
7.8
ns
tPLH
LE
Q
2.1
5
7
2.1
8.2
ns
tPHL
LE
Q
2.7
4.5
6.9
2.7
7.5
ns
tPLH
PRE
Q
1.5
4.5
6.7
1.5
8
ns
tPHL
PRE
Q
2.2
4.5
6.2
2.2
6.4
ns
tPLH
CLR
Q
2.1
4.7
6.5
2.1
7.3
ns
tPHL
CLR
Q
2.4
5.3
7.7
2.4
8.9
ns
tPZH
OE
Q
2.1
5.2
7.6
2.1
9.3
ns
tPZL
OE
Q
4.7
8.1
10.6
4.7
12.2
ns
tPHZ
OE
Q
2.1
4.3
5.8
2.1
6.6
ns
tPLZ
OE
Q
1.5
4.3
6
1.5
6.8
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
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In order to minimize risks associated with the customer's applications, adequate design and operating
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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
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