SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H JULY 1997 REVISED NOVEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Standard '245-Type Pinout
D
5-
Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Shrink
Small-Outline (DBQ), Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages
description
The SN74CBTLV3245A provides eight bits of high-speed bus switching in a standard '245 device pinout. The
low on-state resistance of the switch allows connections to be made with minimal propagation delay.
The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on and A port
is connected to B port. When OE is high, the switch is open and the high-impedance state exists between the
two ports.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3245A is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUT
FUNCTION
OE
FUNCTION
L
A port = B port
H
Disconnect
logic diagram (positive logic)
A1
SW
B1
A8
OE
SW
B8
2
9
19
18
11
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
NC No internal connection
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H JULY 1997 REVISED NOVEMBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simplified schematic, each FET switch
A
(OE)
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I/O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DBQ package
68
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
92
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage
2.3
3.6
V
VIH
High level control input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VIH
High-level control input voltage
VCC = 2.7 V to 3.6 V
2
V
VIL
Low level control input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VIL
Low-level control input voltage
VCC = 2.7 V to 3.6 V
0.8
V
TA
Operating free-air temperature
40
85
C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H JULY 1997 REVISED NOVEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Control inputs
VCC = 3 V
II = 18 mA
1.2
V
VIK
Data inputs
VCC = 3 V,
II = 18 mA
0.8
V
II
VCC = 3.6 V,
VI = VCC or GND
60
A
Ioff
VCC = 0,
VI or VO = 0 to 3.6 V
40
A
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
20
A
ICC
Control inputs
VCC = 3.6 V,
One input at 3 V,
Other inputs at VCC or GND
300
A
Ci
Control inputs
VI = 3 V or 0
4
pF
Cio(OFF)
VO = 3 V or 0,
OE = VCC
9
pF
V
2 3 V
VI = 0
IO = 64 mA
5
8
VCC = 2.3 V,
TYP at VCC = 2 5 V
VI = 0
IO = 24 mA
5
8
r
TYP at VCC = 2.5 V
VI = 1.7 V,
IO = 15 mA
27
40
ron
VI = 0
IO = 64 mA
5
7
VCC = 3 V
VI = 0
IO = 24 mA
5
7
VI = 2.4 V,
IO = 15 mA
10
15
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25
C.
This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
0.2 V
VCC = 3.3 V
0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
tpd
A or B
B or A
0.15
0.25
ns
ten
OE
A or B
1
6
1
4.7
ns
tdis
OE
A or B
1
6.1
1
6.4
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H JULY 1997 REVISED NOVEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V
0.2 V
VCC/2
VCC/2
VCC/2
VCC/2
VOH
VOL
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH 0.15 V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
tPHL
VCC/2
VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VCC/2
tPLH
2
VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034H JULY 1997 REVISED NOVEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V
0.3 V
VCC/2
VCC/2
VCC/2
VCC/2
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.3 V
VOH 0.3 V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
tPHL
VCC/2
VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VCC/2
tPLH
2
VCC
VCC
Figure 2. Load Circuit and Voltage Waveforms
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