SN74LVCH16373A
16 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCAS568L - MARCH 1996 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25
C
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
description/ordering information
This 16-bit transparent D-type latch is designed
for 1.65-V to 3.6-V V
CC
operation.
The SN74LVCH16373A is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube
SN74LVCH16373ADL
LVCH16373A
SSOP - DL
Tape and reel
SN74LVCH16373ADLR
LVCH16373A
-40
C to 85
C
TSSOP - DGG
Tape and reel
SN74LVCH16373ADGGR
LVCH16373A
-40
C to 85
C
TVSOP - DGV
Tape and reel
SN74LVCH16373ADGVR
LDH373A
VFBGA - GQL
Tape and reel
SN74LVCH16373AGQLR
LDH373A
VFBGA - ZQL (Pb-free)
Tape and reel
SN74LVCH16373AZQLR
LDH373A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
SN74LVCH16373A
16 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCAS568L - MARCH 1996 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
terminal assignments
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1LE
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2LE
NC - No internal connection
FUNCTION TABLE
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
GQL OR ZQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
SN74LVCH16373A
16 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCAS568L - MARCH 1996 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1LE
1D1
To Seven Other Channels
1Q1
C1
1D
1
48
47
2
2OE
2LE
2D1
To Seven Other Channels
2Q1
C1
1D
24
25
36
13
Pin numbers shown are for the DGG, DGV, and DL packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1)
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL/ZQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVCH16373A
16 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCAS568L - MARCH 1996 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
1.5
V
VCC = 1.65 V to 1.95 V
0.65
VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
2
V
VCC = 1.65 V to 1.95 V
0.35
VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
High or low state
0
VCC
V
VO
Output voltage
3-state
0
5.5
V
VCC = 1.65 V
-4
IOH
High-level output current
VCC = 2.3 V
-8
mA
IOH
High-level output current
VCC = 2.7 V
-12
mA
VCC = 3 V
-24
VCC = 1.65 V
4
IOL
Low-level output current
VCC = 2.3 V
8
mA
IOL
Low-level output current
VCC = 2.7 V
12
mA
VCC = 3 V
24
t/
v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
-40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LVCH16373A
16 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCAS568L - MARCH 1996 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = -100
A
1.65 V to 3.6 V
VCC-0.2
IOH = -4 mA
1.65 V
1.2
VOH
IOH = -8 mA
2.3 V
1.7
V
VOH
IOH = -12 mA
2.7 V
2.2
V
IOH = -12 mA
3 V
2.4
IOH = -24 mA
3 V
2.2
IOL = 100
A
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
VOL
IOL = 8 mA
2.3 V
0.7
V
VOL
IOL = 12 mA
2.7 V
0.4
V
IOL = 24 mA
3 V
0.55
II
VI = 0 to 5.5 V
3.6 V
5
A
VI = 0.58 V
1.65 V
VI = 1.07 V
1.65 V
VI = 0.7 V
2.3 V
45
II(hold)
VI = 1.7 V
2.3 V
-45
A
II(hold)
VI = 0.8 V
3 V
75
A
VI = 2 V
3 V
-75
VI = 0 to 3.6 V
3.6 V
500
Ioff
VI or VO = 5.5 V
0
10
A
IOZ
VO = 0 to 5.5 V
3.6 V
10
A
ICC
VI = VCC or GND
IO = 0
3.6 V
20
A
ICC
3.6 V
VI
5.5 V
IO = 0
3.6 V
20
A
ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
2.7 V to 3.6 V
500
A
Ci
VI = VCC or GND
3.3 V
5
pF
Co
VO = VCC or GND
3.3 V
6.5
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
This information was not available at the time of publication.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.8 V
0.15 V
VCC = 2.5 V
0.2 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
3.3
3.3
ns
tsu
Setup time, data before LE
1.7
1.7
ns
th
Hold time, data after LE
1.2
1.2
ns
This information was not available at the time of publication.
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