SN74LVTH32373
3.3 V ABT 32 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCBS751A - OCTOBER 2000 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus+
Family
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Supports Unregulated Battery Operation
Down to 2.7 V
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
terminal assignments
1
2
3
4
5
6
A
1Q2
1Q1
1OE
1LE
1D1
1D2
B
1Q4
1Q3
GND
GND
1D3
1D4
C
1Q6
1Q5
1VCC
1VCC
1D5
1D6
D
1Q8
1Q7
GND
GND
1D7
1D8
E
2Q2
2Q1
GND
GND
2D1
2D2
F
2Q4
2Q3
1VCC
1VCC
2D3
2D4
G
2Q6
2Q5
GND
GND
2D5
2D6
H
2Q7
2Q8
2OE
2LE
2D8
2D7
J
3Q2
3Q1
3OE
3LE
3D1
3D2
K
3Q4
3Q3
GND
GND
3D3
3D4
L
3Q6
3Q5
2VCC
2VCC
3D5
3D6
M
3Q8
3Q7
GND
GND
3D7
3D8
N
4Q2
4Q1
GND
GND
4D1
4D2
P
4Q4
4Q3
2VCC
2VCC
4D3
4D4
R
4Q6
4Q5
GND
GND
4D5
4D6
T
4Q7
4Q8
4OE
4LE
4D8
4D7
description/ordering information
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
-40
C to 85
C
LFBGA - GKE
Tape and reel
SN74LVTH32373GKER
HV373
-40
C to 85
C
LFBGA - ZKE (Pb-free)
Tape and reel
SN74LVTH32373ZKER
HV373
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus+ is a trademark of Texas Instruments.
GKE OR ZKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
SN74LVTH32373
3.3 V ABT 32 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCBS751A - OCTOBER 2000 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The SN74LVTH32373 is a 32-bit transparent D-type latch designed for low-voltage (3.3-V) V
CC
operation, but
with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE)
input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
FUNCTION TABLE
(each 8-bit latch)
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
SN74LVTH32373
3.3 V ABT 32 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCBS751A - OCTOBER 2000 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1LE
1D1
To Seven Other Channels
1Q1
C1
1D
A3
A4
A5
A2
2OE
2LE
2D1
To Seven Other Channels
2Q1
C1
1D
H3
H4
E5
E2
3OE
3LE
3D1
To Seven Other Channels
3Q1
C1
1D
J3
J4
J5
J2
4OE
4LE
4D1
To Seven Other Channels
4Q1
C1
1D
T3
T4
N5
N2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . .
Current into any output in the low state, I
O
128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2)
64 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): GKE/ZKE package
40
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVTH32373
3.3 V ABT 32 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCBS751A - OCTOBER 2000 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
5.5
V
IOH
High-level output current
-32
mA
IOL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
ns/V
t/
VCC
Power-up ramp rate
200
s/V
TA
Operating free-air temperature
-40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LVTH32373
3.3 V ABT 32 BIT TRANSPARENT D TYPE LATCH
WITH 3 STATE OUTPUTS
SCBS751A - OCTOBER 2000 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 2.7 V,
II = -18 mA
-1.2
V
VCC = 2.7 V to 3.6 V,
IOH = -100
A
VCC-0.2
VOH
VCC = 2.7 V,
IOH = -8 mA
2.4
V
VOH
VCC = 3 V,
IOH = -32 mA
2
V
VCC = 2.7 V
IOL = 100
A
0.2
VCC = 2.7 V
IOL = 24 mA
0.5
VOL
IOL = 16 mA
0.4
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
V
VCC = 3 V
IOL = 64 mA
0.55
VCC = 0 or 3.6 V,
VI = 5.5 V
10
II
Control inputs
VCC = 3.6 V,
VI = VCC or GND
1
A
II
Data inputs
VCC = 3.6 V
VI = VCC
1
A
Data inputs
VCC = 3.6 V
VI = 0
-5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
VCC = 3 V
VI = 0.8 V
75
II(hold)
Data inputs
VCC = 3 V
VI = 2 V
-75
A
II(hold)
Data inputs
VCC = 3.6 V,
VI = 0 to 3.6 V
500
A
IOZH
VCC = 3.6 V,
VO = 3 V
5
A
IOZL
VCC = 3.6 V,
VO = 0.5 V
-5
A
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care
100
A
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care
100
A
VCC = 3.6 V, IO = 0,
Outputs high
0.38
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
Outputs low
10
mA
ICC
VI = VCC or GND
Outputs disabled
0.38
mA
ICC
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V,
Other inputs at VCC or GND
0.2
mA
Ci
VI = 3 V or 0
3
pF
Co
VO = 3 V or 0
9
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 3.3 V
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
3
3
ns
tsu
Setup time, data before LE
1
0.6
ns
th
Hold time, data after LE
1
1.1
ns
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