TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A JUNE 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Maximum Throughput 400 KSPS
D
Built-In Reference and 8
FIFO
D
Differential/Integral Nonlinearity Error:
1 LSB
D
Signal-to-Noise and Distortion Ratio:
69 dB, f
i
= 12 kHz
D
Spurious Free Dynamic Range: 75 dB,
f
i
= 12 kHz
D
SPI/DSP-Compatible Serial Interfaces With
SCLK up to 20 MHz
D
Single Supply 5 Vdc
D
Analog Input Range 0 V to Supply Voltage
With 500 kHz BW
D
Hardware Controlled and Programmable
Sampling Period
D
Low Operating Current (4 mA at 5.5 V
External Ref,
6 mA at 5.5 V, Internal Ref)
D
Power Down: Software/Hardware
Power-Down Mode (1
A Max, Ext Ref),
Auto Power-Down Mode (1
A, Ext Ref)
D
Programmable Auto-Channel Sweep
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SDO
SDI
SCLK
EOC/(INT)
V
CC
A0
A1
A2
A3
A4
CS
REFP
REFM
FS
PWDN
GND
CSTART
A7
A6
A5
DW OR PW PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDO
SDI
SCLK
EOC/(INT)
V
CC
A0
A1
A2
CS
REFP
REFM
FS
PWDN
GND
CSTART
A3
D OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
description
The TLC2558 and TLC2554 are a family of high-performance, 12-bit low power, 1.6
s, CMOS analog-to-digital
converters (ADC) which operate from a single 5 V power supply. These devices have three digital inputs and
a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial data output
(SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors (SPI
interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the start of a serial data
frame.
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog
multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special
pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be
programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular
among high-performance signal processors. The TLC2558 and TLC2554 are designed to operate with very low
power consumption. The power-saving feature is further enhanced with software/hardware/auto power down
modes and programmable conversion speeds. The converter uses the external SCLK as the source of the
conversion clock to achieve higher (up to 1.6
s when a 20 MHz SCLK is used) conversion speed. There is a
4-V internal reference available. An optional external reference can also be used to achieve maximum flexibility.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A JUNE 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Command
Decode
SDI
CS
FS
EOC/(INT)
Low Power
12-BIT
SAR ADC
Control Logic
CSTART
PWDN
VCC
GND
REFP
Analog
MUX
4 V
Reference
S/H
Conversion
Clock
M
U
X
FIFO
12 Bit
8
CFR
SCLK
SDO
2558
A0
A1
A2
A3
A4
A5
A6
A7
REFM
2554
A0
X
A1
X
A2
X
A3
X
CMR (4 MSBs)
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
20-TSSOP
(PW)
20-SOIC
(DW)
16-SOIC
(D)
16-TSSOP
(PW)
0
C to 70
C
TLC2558CPW
TLC2558CDW
TLC2554CD
TLC2554CPW
40
C to 85
C
TLC2558IPW
TLC2558IDW
TLC2554ID
TLC2554IPW
TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A JUNE 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TLC2554
TLC2558
A0
A0
A1
A1
A2
A2
A3
A3
A4
A5
A6
A7
6
7
8
9
6
7
8
9
10
11
12
13
I
Analog signal inputs. The analog inputs are applied to these terminals and are internally
multiplexed. The driving source impedance should be less than or equal to 1 k
.
For a source impedance greater than 1 k
, use the asynchronous conversion start signal CSTART
(CSTART low time controls the sampling period) or program long sampling period to increase the
sampling time.
CS
16
20
I
Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter, enables SDI,
and removes SDO from 3-state within a maximum setup time. SDI is disabled within a setup time
after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS whichever
happens first. SDO is 3-stated after the rising edge of CS.
CS can be used as the FS pin when a dedicated serial port is used.
CSTART
10
14
I
This terminal controls the start of sampling of the analog input from a selected multiplex channel.
A high-to-low transition starts sampling of the analog input signal. A low-to-high transition puts the
S/H in hold mode and starts the conversion. This input is independent from SCLK and works when
CS is high (inactive). The low time of CSTART controls the duration of the sampling period of the
converter (extended sampling).
Tie this terminal to VCC if not used.
EOC/(INT)
4
4
O
End of conversion or interrupt to host processor.
[PROGRAMMED AS EOC]: This output goes from a high-to-low logic level at the end of the
sampling period and remains low until the conversion is complete and data are ready for transfer.
EOC is used in conversion mode 00 only.
[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to the
host processor. The falling edge of INT indicates data are ready for output. The following CS
or
FS
clears INT. The falling edge of INT puts SDO back to 3-state even if CS is still active.
FS
13
17
I
DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If FS
remains low at the falling edge of CS, SDI is not enabled. A high-to-low transition on the FS input
resets the internal 4-bit counter and enables SDI within a maximum setup time. SDI is disabled
within a setup time after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of
CS whichever happens first. SDO is 3-stated after the 16th bit is presented.
Tie this terminal to VCC if not used.
GND
11
15
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with
respect to GND.
PWDN
12
16
I
Both analog and reference circuits are powered down when this pin is at logic zero. The device can
be restarted by active CS or CSTART after this pin is pulled back to logic one.
SCLK
3
3
I
Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is used
to clock the input SDI to the input register. It is also used as the source of the conversion clock.
SDI
2
2
I
Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,
D(1512) are decoded as one of the 16 commands (12 only for the TLC2554). All trailing blanks
are filled with zeros. The configure write commands require an additional 12 bits of data.
When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS and is
shifted in on the rising edges of SCLK (after CS
).
When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected after the
falling edge of FS and is shifted in on the falling edges of SCLK.
TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A JUNE 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TLC2554
TLC2558
SDO
1
1
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state
when CS is high and after the CS falling edge and until the MSB (D15) is presented. The output
format is MSB (D15) first.
When FS is not used (FS = 1 at the falling edge of CS), the MSB (D15) is presented to the SDO
pin after the CS falling edge, and successive data are available at the rising edge of SCLK.
When FS is used (FS = 0 at the falling edge of CS), the MSB (D15) is presented to SDO after the
falling edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK.
(This is typically used with an active FS from a DSP.)
For conversion and FIFO read cycles, the first 12 bits are the result from the previous conversion
(data) followed by 4 trailing zeros. The first four bits from SDO for CFR read cycles should be
ignored. The register content is in the last 12 bits. SDO is 3 stated after the 16th bit.
REFM
14
18
I
External reference input or internal reference decoupling.
REFP
15
19
I
External reference input or internal reference decoupling. (Shunt capacitors of 10
F and 0.1
F
between REFP and REFM.) The maximum input voltage range is determined by the difference
between the voltage applied to this terminal and the REFM terminal when an external reference
is used.
VCC
5
5
I
Positive supply voltage
detailed description
analog inputs and internal test voltages
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection
resulting from channel switching.
pseudo-differential/single-ended input
All analog inputs can be programmed as single-ended or pseudo-differential mode. Pseudo-differential mode
is enabled by setting CFR.D7 1. Only three analog input channels (or seven channels for TLC2558) are
available for TLV2554 since one input (A1 for TLC2554 or A2 for TLC2558) is used as the MINUS input when
pseudo-differential mode is used. The minus input pin can have a maximum
0.2 V ripple. This is normally used
for ground noise rejection.
converter
The TLC2554/58 uses a 12-bit successive approximation ADC and 2-bit resistor string. The CMOS threshold
detector in the successive-approximation conversion system determines each bit by examining the charge on
a series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog
input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the
capacitors to the input voltage.
TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A JUNE 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
converter (continued)
SC
Threshold
Detector
Node
512
VI
To Output
Latch
ST
ST
ST
ST
ST
ST
ST
1
1
2
4
8
256
512
REF
REF
REF
REF
REF
REF
REF+
REF+
REF+
REF+
REF+
REF+
2-Bit
R-String
DAC
Figure 1. Simplified Model of the Successive-Approximation System
In the next phase of the conversion process the threshold detector begins identifying bits by identifying the
charge (voltage) on each capacitor relative to the reference (REFM) voltage. In the switching sequence, ten
capacitors are examined separately until all ten bits are identified and the charge-convert sequence is repeated.
In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 512). Node
512 of this capacitor is switched to the REFP voltage, and the equivalent nodes of all the other capacitors on
the ladder are switched to REFM. If the voltage at the summing node is greater than the trip point of the threshold
detector (approximately one-half the V
CC
voltage), a bit 0 is placed in the output register and the 512-weight
capacitor is switched to REFM. If the voltage at the summing node is less than the trip point of the threshold
detector, a bit 1 is placed in the register. The 512-weight capacitor remains connected to REFP through the
remainder of the successive-approximation process. The process is repeated for the 1024-weight capacitor,
the 128-weight capacitor, and so forth down the line until all bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
serial interface
INPUT DATA FORMAT
MSB
LSB
D15D12
D11D0
Command
Configuration data field
Input data is binary. All trailing blanks can be filled with zeros.
OUTPUT DATA FORMAT READ CFR
MSB
LSB
D15D12
D11D0
Don't care
Register content
OUTPUT DATA FORMAT CONVERSION/READ FIFO
MSB
LSB
D15D4
D3D0
Conversion result
All zeros
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