TLK2201B, TLK2201BI
ETHERNET TRANSCEIVERS
SLLS585 - NOVEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
1 to 1.6 Gigabits Per Second (Gbps)
Serializer/Deserializer (TLK2201B)
D
1.2 to 1.6 Gigabits Per Second (Gbps)
Serializer/Deserializer (TLK2201BI)
D
Low Power Consumption <200 mW
at 1.25 Gbps
D
LVPECL Compatible Differential I/O on High
Speed Interface
D
Single Monolithic PLL Design
D
Support For 10 Bit Interface or Reduced
Interface 5 Bit DDR (Double Data Rate)
Clocking
D
Receiver Differential Input Thresholds
200 mV Minimum
D
Industrial Temperature Range From -40
C
to 85
C (TLK2201BI)
D
IEEE 802.3 Gigabit Ethernet Compliant
D
Advanced 0.25
m CMOS Technology
D
No External Filter Capacitors Required
D
Comprehensive Suite of Built-In Testability
D
IEEE 1149.1 JTAG Support
D
2.5-V Supply Voltage for Lowest Power
Operation
D
3.3-V Tolerant on LVTTL Inputs
D
Hot Plug Protection
D
64-Pin VQFP With Thermally Enhanced
Package (PowerPAD
)
17 18 19
JTDI
SYNC/PASS
GND
RD0
RD1
RD2
VDD
RD3
RD4
RD5
RD6
VDD
RD7
RD8
RD9
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
TD0
TD1
TD2
VDD
TD3
TD4
TD5
TD6
VDD
TD7
TD8
TD9
GND
MODESEL
PRBSEN
21 22 23 24
VDD
RXP
63 62 61 60 59
64
58
TXP
TXN
VDDA
VDDA
GNDA
VDDA
JTRST
N
LOS
JTDO
ENABLE
VDD
LOOPEN
VDD
GND
REFCLK
VDD
SYNCEN
GND
56 55 54
57
25 26 27 28 29
53 52
TESTEN
VDDA
RXN
51 50 49
30 31 32
RBC1
RBC0
R
BCMODE
GNDA
JTMS
TCK
GNDP
LL
VDD
VDDPLL
description
The TLK2201B and TLK2201BI gigabit ethernet transceivers provide for ultrahigh-speed full-duplex
point-to-point data transmissions. These devices are based on the timing requirements of the 10-bit interface
specification by the IEEE 802.3 Gigabit Ethernet specification. The TLK2201B supports data rates from 1.0
Gbps through 1.6 Gbps and the TLK2201BI supports data rates from 1.2 Gbps through 1.6 Gbps.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
TLK2201B, TLK2201BI
ETHERNET TRANSCEIVERS
SLLS585 - NOVEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The primary application of these devices is to provide building blocks for point-to-point baseband data
transmission over controlled impedance media of 50
or 75
. The transmission media can be printed-circuit
board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The TLK2201B and TLK2201BI perform the data serialization, deserialization, and clock extraction functions
for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps
of data bandwidth over a copper or optical media interface.
The TLK2201B and TLK2201BI support both the defined 10-bit interface (TBI) and a reduced 5-bit interface
utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit
wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially
at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and
deserializes the data, outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and
falling edge of the reference clock. The data is clocked most significant bit first, (bits 0 - 4 of the 8b/10b encoded
data) on the rising edge of the clock and the least significant bits (bits 5 - 9 of the 8b/10b encoded data) are
clocked on the falling edge of the clock.
The TLK2201B and TLK2201BI provide a comprehensive series of built-in tests for self-test purposes including
loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port
is also supported.
The TLK2201B and TLK2201BI are housed in a high performance, thermally enhanced, 64-pin VQFP
PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note
that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical
conductor. It is recommended that the TLK2201B and TLK2201BI PowerPADs
be soldered to the thermal land
on the board.
The TLK2201B is characterized for operation from 0
C to 70
C. The TLK2201BI is characterized for operation
from -40
C to 85
C.
The TLK2201B and TLK2201BI use a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply
the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.
The TLK2201B and TLK2201BI are designed to be hot plug capable. A power-on reset causes RBC0, RBC1,
the parallel output signal terminals, TXP, and TXN to be held in high-impedance state.
differences between TLK2201B, TLK2201BI, and TNETE2201
The TLK2201B and TLK2201BI are the functional equivalent of the TNETE2201. There are several differences
between the devices as noted below. Refer to Figure 12 in the application information section for an example
of a typical application circuit.
D
The V
CC
is 2.5 V for the TLK2201B and TLK2201BI vs 3.3 V for TNETE2201.
D
The PLL filter capacitors on pins 16, 17, 48, and 49 of the TNETE2201 are no longer required. The
TLK2201B and TLK2201BI uses these pins to provide added test capabilities. The capacitors, if present,
do not affect the operation of the device.
D
No pulldown resistors are required on the TXP/TXN outputs.
TLK2201B, TLK2201BI
ETHERNET TRANSCEIVERS
SLLS585 - NOVEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
block diagram
2:1
MUX
PRBS
Generator
10 Bit
Registers
TD(0-9)
PRBSEN
LOOPEN
Parallel to
Serial
Phase Generator
Clock
REFCLK
Control
Logic
MODESEL
ENABLE
TESTEN
Interpolator
and
Clock Extraction
PRBS
Verification
Serial to Parallel
and
Comma Detect
Clock
RBC1
RBC0
SYNC/PASS
RD(0-9)
SYNCEN
RBCMODE
JTAG
Control
Register
JTMS
JTRSTN
JTDI
TCK
JTDO
2:1
MUX
2:1
MUX
Clock
Data
TXP
TXN
RXP
RXN
LOS
detailed description
data transmission
These devices support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR
clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is
selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0-TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bit 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0-TD4. In this mode data
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and
sent to the serializer. The rising edge REFCLK clocks in bit 0-4, and the falling edge of REFCLK clocks in bits
5-9. ( Bit 0 is the first bit transmitted).
TLK2201B, TLK2201BI
ETHERNET TRANSCEIVERS
SLLS585 - NOVEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
transmission latency
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of
bit 9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The
minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times.
10 Bit Code
TXP, TXN
TD(0-9)
REFCLK
td(Tx latency)
10 Bit Code
b9
Figure 1. Transmitter Latency Full Rate Mode
data reception
The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated
clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and
presented to the protocol controller along with receive byte clocks (RBC0, RBC1).
receiver clock select mode
There are two modes of operation for the parallel busses. 1)The 10-bit (TBI) mode and 2) 5-bit (DDR) mode.
When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal.
1) Full-rate clock on RBC0 and 2) Half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate
clock is available on RBC0; refer to Table 1.
Table 1. Mode Selection
MODESEL
RBCMODE
MODE
FREQUENCY
(TLK2201B)
FREQUENCY
(TLK2201BI)
0
0
TBI half-rate
100-125 MHz
120-125 MHz
0
1
TBI full-rate
100-160 MHz
120-160 MHz
1
0
DDR
100-125 MHz
120-125 MHz
1
1
DDR
100-125 MHz
120-125 MHz
In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate
at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data
is output with respect to the two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the
parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received
data valid on the rising edge of RBC1. Refer to the timing diagram shown in Figure 2.
TLK2201B, TLK2201BI
ETHERNET TRANSCEIVERS
SLLS585 - NOVEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receiver clock select mode (continued)
td(S)
td(S)
td(H)
td(H)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
RBC0
RBC1
SYNC
RD(0-9)
Figure 2. Synchronous Timing Characteristics Waveforms (TBI half-rate mode)
In the normal-rate mode, only RBC0 is used and operates at full data rate (i.e., 1.25 Gbps data rate produces
a 125 MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode.
Refer to the timing diagram shown in Figure 3.
td(H)
td(S)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
RBC0
SYNC
RD(0-9)
Figure 3. Synchronous Timing Characteristics Waveforms (TBI full-rate mode)
In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1
is low impedance. The data is clocked bit-0 first, and aligned to the rising edge of RBC0. Refer to the timing
diagram shown in Figure 4.
K28.5
DXX.X
td(S)
td(H)
td(S)
td(H)
K28.5
DXX.X
DXX.X
DXX.X
DXX.X
DXX.X
K28.5
K28.5
DXX.X
Bits 0-4 Bits 5-9
RBC0
SYNC
RD(0-4)
Figure 4. Synchronous Timing Characteristics Waveforms (DDR mode)
The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset.
The received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream,
0.02%
(200 PPM) for proper operation (see page 11).
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