TLV320AIC33
SLAS480 -- MAY 24, 2005
PRELIMINARY INFORMATION REV.17
1
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
www.ti.com
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appear at the end of this data sheet.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
Copyright
200
5, Texas Instruments Incorporated
Low Power Stereo Audio Codec for Portable Audio/Telephony
FEATURES
STEREO AUDIO DAC
103dB-A
SIGNAL-TO-NOISE
RATIO
16/20/24/32-BIT
DATA
SUPPORTS RATES FROM 8-kHz to 96-kHz
3D/BASS/TREBLE/EQ/DE-EMPHASIS
EFFECTS
STEREO AUDIO ADC
92dB-A
SIGNAL-TO-NOISE
RATIO
SUPPORTS RATES FROM 8-kHz TO 96-kHz
TEN AUDIO INPUT PINS
PROGRAMMABLE IN SINGLE-ENDED OR FULLY
DIFFERENTIAL
CONFIGURATIONS
TRI-STATE CAPABILITY FOR FLOATING INPUT
CONFIGURATIONS
SEVEN AUDIO OUTPUT DRIVERS
STEREO 8-OHM 325mW/CHANNEL SPEAKER
DRIVE
CAPABILITY
STEREO FULLY-DIFFERENTIAL OR SINGLE-
ENDED HEADPHONE DRIVERS
FULLY DIFFERENTIAL STEREO LINE OUTPUTS
FULLY DIFFERENTIAL MONO OUTPUT
LOW POWER: 14mW STEREO 48-kHz PLAYBACK
WITH 3.3V ANALOG SUPPLY
PROGRAMMABLE INPUT/OUTPUT ANALOG GAINS
AUTOMATIC GAIN CONTROL (AGC) FOR RECORD
PROGRAMMABLE MICROPHONE BIAS LEVEL
PROGRAMMABLE PLL FOR FLEXIBLE CLOCK
GENERATION
CONTROL BUS SELECTABLE SPI OR I2C
AUDIO SERIAL DATA BUS SUPPORTS I2S,
LEFT/RIGHT-JUSTIFIED, DSP, AND TDM MODES
ALTERNATE SERIAL PCM/I2S DATA BUS FOR EASY
CONNECTION
TO
BLUETOOTH MODULE
DIGITAL MICROPHONE INPUT SUPPORT
EXTENSIVE MODULAR POWER CONTROL
POWER SUPPLIES:
ANALOG: 2.7V 3.6V
DIGITAL CORE: 1.525V 1.95V
DIGITAL I/O: 1.1V 3.6V
PACKAGES: 5X5MM 80-BGA
7X7MM
48-QFN
DESCRIPTION
The TLV320AIC33 is a low power stereo audio codec with
stereo headphone amplifier, as well as multiple inputs and
outputs programmable in single-ended or fully-differential
configurations. Extensive register-based power control is
included, enabling stereo 48-kHz DAC playback as low as
15mW(TBD) from a 3.3V analog supply, making it ideal for
portable battery-powered audio and telephony applications.
The record path of the TLV320AIC33 contains integrated
microphone bias, digitally controlled stereo microphone pre-
amp, and automatic gain control (AGC), with mix/mux
capability among the multiple analog inputs. The playback
path includes mix/mux capability from the stereo DAC and
selected inputs, through programmable volume controls, to
the various outputs.
The TLV320AIC33 contains four high-power output drivers as
well as three fully differential output drivers. The high-power
output drivers are capable of driving a variety of load
configurations, including up to four channels of single-ended
16-
headphones using ac-coupling capacitors, or stereo 16-
headphones in a cap-less output configuration. In addition,
pairs of drivers can be used to drive 8-
speakers in a BTL
configuration at 325mW per channel.
The stereo audio DAC supports sampling rates from 8-kHz to
96-kHz and includes programmable digital filtering in the DAC
path for 3D, bass, treble, midrange effects, speaker
equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48-
kHz rates. The stereo audio ADC supports sampling rates
from 8-kHz to 96-kHz and is preceded by programmable gain
amplifiers providing up to +59.5-dB analog gain for low-level
microphone inputs.
The serial control bus supports SPI or I2C protocols, while the
serial audio data bus is programmable for I2S, left/right-
justified, DSP, or TDM modes. A highly programmable PLL is
included for flexible clock generation and support for all
standard audio rates from a wide range of available MCLKs,
varying from 2-MHz to 50-MHz, with special attention paid to
the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-
MHz, and 19.68-MHz system clocks.
The TLV320AIC33 operates from an analog supply of
2.7V 3.6V, a digital core supply of 1.525V 1.95V, and a
digital I/O supply of 1.1V 3.6V. The device is available in
5x5mm 80-ball u*jr BGA and 7x7mm 48-lead QFN.
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
2
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
www.ti.com
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
Copyright
2004, Texas Instruments Incorporated
SIMPLIFIED BLOCK DIAGRAM
LINE_OUT_L+
LINE_OUT_L-
LINE_OUT_R+
LINE_OUT_R-
MONO_OUT+
MONO_OUT-
HPR+
HPL-/HPLCOM
HPL+
MIC2/LINE2L+
MIC2/LINE2L-
MIC1/LINE1L+
MIC1/LINE1L-
MIC1/LINE1R+
MIC1/LINE1R-
MIC3/LINE3R
MIC3/LINE3L
PGA
0/+59.5dB
0.5dB
steps
ADC
ADC
Audio Serial
Bus
DAC
L
DAC
R
DI
N
DOU
T
BC
LK
WC
LK
SPI / I2C Serial Control
Bus
SELEC
T
CS
E
L
/
I
2
C_
ADR
0
SC
L
K
/I2
C_
AD
R1
MO
SI/GPIO
MI
SO/GPIO
Audio Clock
Generation
MC
L
K
GPIO_1
GPIO_2
Bias/
Reference
MI
CB
IA
S
Voltage Supplies
A
V
DD
_D
AC
A
VSS_D
A
C
DR
V
D
D
DR
V
S
S
DV
D
D
D
VSS
IOV
D
D
Volume Ctl
& Effects
Volume Ctl
& Effects
DR
V
D
D
DR
V
S
S
SC
L/GPIO
SD
A/
GPIO
A
V
DD
_A
DC
A
VSS_A
D
C
R
ESETB
MI
CD
ET
MIC2/LINE2R-
MIC2/LINE2R+
+
+
VCM
+
+
+
HPR-/HPRCOM/
SPKFC
+
VCM
+
PGA
0/+59.5dB
0.5dB
steps
+
+
Figure 1. Simplified codec block diagram
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
3
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
www.ti.com
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appear at the end of this data sheet.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
Copyright
2004, Texas Instruments Incorporated
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE
PACKAGE
DESIGNATOR
OPERATING
TEMPERATURE
RANGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
TLV320AIC33IZQE Trays??,
xx
BGA-80 ZQE
TLV320AIC33IZQER
Tape and Reel, 2000
TLV320AIC33IRGZ Rails,
52
TLV320AIC33
QFN-48 RGZ
-40C to 85C
TLV320AIC33IRGZR
Tape and Reel, 2000
PIN ASSIGNMENTS
13
12
1
24
25
36
37
48
4
1
2
3
5
6
7
8
9
A
B
C
D
E
F
G
H
J
48-lead QFN Package (Bottom view)
5x5mm 80-Ball BGA Package (Bottom View)
(Not to scale)
(Note: Shaded balls on BGA package are not connected to the die, but are electrically connected to
each other.)
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
4
www.ti.com
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
PIN DESCRIPTION
BGA
BALL
QFN PIN
NUMBER
PIN NAME
DESCRIPTION
A2
13
MICBIAS
Microphone Bias Voltage Output
A1
14
MIC3R
MIC3 Input (Right or Multifunction)
C2,D2
15
AVSS_ADC
Analog ADC Ground Supply, 0V
B1,C1
16,17
VDDA1
ADC Analog and Output Driver Voltage Supply, 2.7V 3.6V
D1
18
HPLOUT
High Power Output Driver (Left Plus)
E1
19
HPLCOM
High Power Output Driver (Left Minus or Multifunctional)
E2,F2
20,21
DRVSS
Analog Output Driver Ground Supply, 0V
F1
22
HPRCOM
High Power Output Driver (Right Minus or Multifunctional)
G1
23
HPROUT
High Power Output Driver (Right Plus)
H1
24
VDDA1
ADC Analog and Output Driver Voltage Supply, 2.7V 3.6V
J1
25
AVDDA2
Analog DAC Voltage Supply, 2.7V 3.6V
G2,H2
26
AVSS_DAC
Analog DAC Ground Supply, 0V
J2
27
MONO_LOP
Mono Line Output (Plus)
J3
28
MONO_LOM
Mono Line Output (Minus)
J4
29
LEFT_LOP
Left Line Output (Plus)
J5
30
LEFT_LOM
Left Line Output (Minus)
J6
31
RIGHT_LOP
Right Line Output (Plus)
J7
32
RIGHT_LOM
Right Line Output (Minus)
H8 33
/RESET Reset
J8 34
GPIO2
General Purpose Input/Output #2 (Input/Output) / Digital Microphone
Data Input / PLL Clock Input / Audio Serial Data Bus Bit Clock
Input/Output
J9 35
GPIO1
General Purpose Input/Output #1 (Input/Output) / PLL/Clock Mux Output
/ Short Circuit Interrupt / AGC Noise Flag / Digital Microphone Clock /
Audio Serial Data Bus Word Clock Input/Output
H9
36
DVDD
Digital Core Voltage Supply, 1.525V 1.95V
G8
37
MCLK
Master Clock Input
G9
38
BCLK
Audio Serial Data Bus Bit Clock (Input/Output)
F9
39
WCLK
Audio Serial Data Bus Word Clock (Input/Output)
E9
40
DIN
Audio Serial Data Bus Data Input (Input)
F8
41
DOUT
Audio Serial Data Bus Data Output (Output)
D9
42
DVSS
Digital Core / I/O Ground Supply, 0V
E8
43
SELECT
Select Pin (SPI vs I2C Control Mode)
C9
44
IOVDD
I/O Voltage Supply, 1.1V 3.6V
B8
45
MFP0
Multifunction pin #0 - SPI Chip Select / GPI / I2C Address Pin #0
B9
46
MFP1
Multifunction pin #1 - SPI Serial Clock / GPI / I2C Address Pin #1
A8
47
MFP2
Multifunction pin #2 - SPI MISO Slave Serial Data Output / GPO
A9 48
MFP3
Multifunction pin #3 - SPI MOSI Slave Serial Data Input / GPI / Audio
Serial Data Bus Data Input
C8
1
SCL
I2C Serial Clock / GPIO
D8
2
SDA
I2C Serial Data Input/Output / GPIO
A7
NC
No
Connect
A6
3
LINE1LP
MIC1 or Line1 Analog Input (Left Plus or Multifunction)
TLV320AIC33
MAY 6, 2005
PRELIMINARY INFORMATION REV.17
5
www.ti.com
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
A5
4
LINE1LM
MIC1 or Line1 Analog Input (Left Minus or Multifunction)
B7
5
LINE1RP
MIC1 or Line1 Analog Input (Right Plus or Multifunction)
B6
6
LINE1RM
MIC1 or Line1 Analog Input (Right Minus or Multifunction)
A4
7
LINE2LP
MIC2 or Line2 Analog Input (Left Plus or Multifunction)
B5
8
LINE2LM
MIC2 or Line2 Analog Input (Left Minus or Multifunction)
B4
9
LINE2RP
MIC2 or Line2 Analog Input (Right Plus or Multifunction)
A3
10
LINE2RM
MIC2 or Line2 Analog Input (Right Minus or Multifunction)
B3
11
MIC3L
MIC3 Input (Left or Multifunction)
B2 12
MICDET Microphone
Detect
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(1)
RATINGS
VDDA1 to VSS, VDDA2 to AVSS_DAC
-0.3V to 3.9V
VDDA1 to DRVSS
-0.3V to 3.9V
IOVDD to DVSS
-0.3V to 3.9V
DVDD to DVSS
-0.3V to 2.5V
VDDA2 to VDDA1
-0.1V to 0.1V
Digital Input Voltage to DVSS
-0.3V to IOVDD+0.3V
Analog Input Voltage to AVSS
-0.3V to AVDD+0.3V
Operating temperature range
-40
C to +85
C
Storage temperature range
-65
C to +105
C
Junction temperature (T
J
Max)
+105
C
Power dissipation
(T
J
Max T
A
) /
JA
BGA package
JA
Thermal impedance
TBD
Soldering vapor phase (60 sec)
TBD
Lead temperature
Infrared (15 sec)
TBD
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
"recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability
.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Analog supply voltage VDDA2, VDDA1
(2)
2.7 3.3 3.6 V
Digital core supply voltage DVDD
(2)
1.525
1.8
1.95
V
Digital I/O supply voltage IOVDD
(2)
1.1 1.8 3.6 V
Analog full-scale 0dB input voltage (VDDA2, VDDA1 = 3.3V)
0.707
V
RMS
Stereo line output load resistance
10 k
Stereo headphone output load resistance
TBD 16
Digital output load capacitance
10
pF
Operating free-air temperature, T
A
-40 +85
C
(2) Analog
voltage values are with respect to AVSS_ADC, AVSS_DAC, DRVSS; digital voltage values are with respect to
DVSS
.
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