TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS137E JANUARY 1991 REVISEDJUNE 1995
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
D
Organization
TM124MBK36B . . . 1 048 576
36
TM248NBK36B . . . 2 097 152
36
D
Single 5-V Power Supply (
10% Tolerance)
D
72-pin Leadless Single In-Line Memory
Module (SIMM) for Use With Sockets
D
TM124MBK36BUtilizes Eight 4-Megabit
DRAMs in Plastic Small-Outline J-Lead
(SOJ) Packages and One 4-Megabit
Quad-CAS DRAM in a Plastic Small-Outline
J-Lead (SOJ) Package
D
TM248NBK36BUtilizes Sixteen 4-Megabit
DRAMs in Plastic Small-Outline J-Lead
(SOJ) Packages and Two 4-Megabit
Quad-CAS DRAMs in Plastic Small-Outline
J-Lead (SOJ) Packages
D
Long Refresh Period
16 ms (1024 Cycles)
D
All Inputs, Outputs, Clocks Fully TTL
Compatible
D
3-State Output
D
Common CAS Control for Nine Common
Data-In and Data-Out Lines, in Four Blocks
D
Enhanced Page Mode Operation with
CAS-Before-RAS ( CBR ), RAS-Only, and
Hidden Refresh
D
Presence Detect
D
Performance Ranges:
ACCESS
ACCESS ACCESS READ
TIME
TIME
TIME
OR
tRAC
tAA
tCAC
WRITE
CYCLE
(MAX) (MAX)
(MAX)
(MIN)
'124MBK36B-60 60 ns
30 ns
15 ns
110 ns
'124MBK36B-70 70 ns
35 ns
18 ns
130 ns
'124MBK36B-80 80 ns
40 ns
20 ns
150 ns
'248NBK36B-60
60 ns
30 ns
15 ns
110 ns
'248NBK36B-70
70 ns
35 ns
18 ns
130 ns
'248NBK36B-80
80 ns
40 ns
20 ns
150 ns
D
Low Power Dissipation
D
Operating Free-Air Temperature Range
0
C to 70
C
D
Gold-Tabbed Versions Available:
TM124MBK36B
TM248NBK36B
D
Tin-Lead (Solder) Tabbed Versions
Available:
TM124MBK36R
TM248NBK36R
description
TM124MBK36B
The TM124MBK36B is a dynamic random-access memory (DRAM) organized as four times 1 048 576
9
(bit 9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is
composed of eight TMS44400DJ, 1 048 576
4-bit DRAMs, each in 20/26-lead plastic small-outline J-lead
packages (SOJs), and one TMS44460DJ, 1 048 576
4-bit Quad-CAS DRAM in a 24/26-lead plastic
small-outline J-lead package (SOJ), mounted on a substrate with decoupling capacitors. Each TMS44400DJ
and TMS44460DJ is described in the TMS44400 or TMS44460 data sheet, respectively.
The TM124MBK36B is available in the single-sided BK leadless module for use with sockets.
The TM124MBK36B features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation
from 0
C to 70
C.
TM248NBK36B
The TM248NBK36B is a DRAM organized as four times 2 097 152
9 (bit 9 is generally used for parity) in a
72-pin leadless SIMM. The SIMM is composed of sixteen TMS44400DJ, 1 048 576
4-bit DRAMs, each in
20/26-lead plastic small-outline J-lead packages (SOJs), and two TMS44460DJ, 1 048 576
4-bit Quad-CAS
DRAMs, each in a 24/26-lead plastic small-outline J-lead package (SOJ), mounted on a substrate with
decoupling capacitors. Each TMS44400DJ and TMS44460DJ is described in the TMS44400 and TMS44460
data sheet, respectively.
Copyright
1995, Texas Instruments Incorporated
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS137E JANUARY 1991 REVISEDJUNE 1995
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
TM248NBK36B (continued)
The TM124NBK36B is available in the double-sided BK leadless module for use with sockets.
The TM124NBK36B features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation
from 0
C to 70
C
operation
TM124MBK36B
The TM124MBK36B operates as eight TMS44400DJs and one TMS44460DJ connected as shown in the
functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by
RAS2. To ensure proper parity bit operation all memory accesses should include a RAS2 pulse. Refer to the
TMS44400 and TMS44460 data sheets for details of operation. The common I/O feature dictates the use of
early write cycles to prevent contention on D and Q.
TM248NBK36B
The TM248NBK36B operates as sixteen TMS44400DJs and two TMS44460DJs connected as shown in the
functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by
RAS2 on side 1 and RAS3 on side 2. To ensure proper parity bit operation, all memory accesses should include
a RAS2 or RAS3 pulse. Refer to the TMS44400 and TMS44460 data sheets for details of operation. The
common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT
DYNAMIC RAM MODULE
SMMS137E JANUARY 1991 REVISEDJUNE 1995
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Table 1. Connection Table
DATA BLOCK
RASx
CASx
DATA BLOCK
SIDE 1
SIDE 2
CASx
DQ0 DQ7
DQ8
RAS0
RAS2
RAS1
RAS3
CAS0
CAS0
DQ9 DQ16
DQ17
RAS0
RAS2
RAS1
RAS3
CAS1
CAS1
DQ18 DQ25
DQ26
RAS2
RAS2
RAS3
RAS3
CAS2
CAS2
DQ27 DQ34
DQ35
RAS2
RAS2
RAS3
RAS3
CAS3
CAS3
Side 2 applies to the TM248NBK36B only.
single-in-line memory module and components
PC substrate: 1,27
0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36B and TM248NBK36B: Nickel plate and gold plate over copper
Contact area for TM124MBK36R and TM248NBK36R: Nickel plate and tin-lead over copper
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