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Электронный компонент: TNETX3270

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TNETX3270
ThunderSWITCH
TM
24/3 ETHERNET
TM
SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B NOVEMBER 1997 REVISED APRIL 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Port Configurations:
Twenty-Four 10-Mbit/s Ports
Ports Arranged in Three Groups of Eight
Ports in a Multiplexed Interface
Direct Multiplexer Interface to
TNETE2008
Full and Half Duplex
Half-Duplex Collision-Based Flow
Control
Full-Duplex IEEE Std 802.3x Flow Control
Interoperable Support for IEEE
Std 802.1Q VLAN
Speed, Duplex, and Pause
Autonegotiation With Physical Layer
(PHY)
Three 10-/100-Mbit/s Ports
Direct Interface to TNETE2101
Full and Half Duplex
Half-Duplex Collision-Based Flow
Control
Full-Duplex IEEE Std 802.3x Flow Control
Interoperable Support for IEEE
Std 802.1Q VLAN
Pretagging Support
D
Port Trunking and Load Sharing
D
LED Indication of Port Status
D
SDRAM Interface
Direct Interface to 8-Bit/Word and
16-Bit/Word, 16-Mbit, and 64-Mbit
SDRAMs
32-Bit-Wide Data Bus
Up to 32 Mbytes Supported
83.33-MHz SDRAM Clock
12-ns (12) SDRAMs Required
D
Remote Monitoring (RMON) Support
Groups 1, 2, 3, and 9
D
Direct I/O (DIO) Management Interface
Eight Bits Wide
CPU Access to Statistics, Registers, and
Management Information Bases (MIBs)
Internal Network Management Port
Forwards Spanning-Tree Packets to CPU
Serial Media-Independent Interface (MII)
for PHY Control
D
EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)
D
Internal Address-Lookup/Frame-Routing
Engine
Interoperable Support for IEEE
Std 802.1Q VLAN
Supports IEEE Std 802.1D Spanning Tree
Thirty-Two Assignable Virtual LANs
(VLANs)
Multiple Forwarding Modes
2K Total Addresses Supported
Port Mirroring
D
IEEE Std 1149.1 (JTAG) Interface (3.3-V
Signals)
D
2.5-V Process With 3.3-V-Drive I/O
D
Packaged in 240-Terminal Plastic Quad
Flatpack
Eight Ports
(1623)
10 Mbit/s
Controller (MAC)
Controller (MAC)
Controller (MAC)
TAP
(JTAG)
Address
Compare
Statistics
Storage
MIB
Three Ports
(2426)
10/100 Mbit/s
Network
Statistics
Logic
Data Path
LED
Interface
CPU
Interface
SDRAM
Controller
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
MUX
Controller (MAC)
Controller (MAC)
MII
MII
MII
Eight Ports
(0815)
10 Mbit/s
Eight Ports
(0007)
10 Mbit/s
Queue
Manager
EEPROM
Interface
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
MUX
Controller (MAC)
Controller (MAC)
MUX
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI and ThunderSWITCH are trademarks of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching
TM
.
TNETX3270
ThunderSWITCH
TM
24/3 ETHERNET
TM
SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B NOVEMBER 1997 REVISED APRIL 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description
The TNETX3270 provides highly integrated switching solutions that allow network designers to lower overall
system costs. Based on Texas Instruments (TI
TM
) ThunderSWITCH
TM
architecture, the TNETX3270 design
integrates 24 full-duplex 10-Mbit/s ports and 3 full-duplex 10-/100-Mbit/s ports, as well as an address-lookup
engine, all in a single 240-pin package. All ports on the TNETX3270 are designed to support multiple addresses,
cut-through or store-and-forward modes of operation, and VLAN. The 10-/100-Mbit/s ports have
media-independent interface (MII)-compatible interfaces and can be configured to work as MII uplinks to
high-speed switching fabrics. All three of the 10-/100-Mbit/s ports can be logically combined into a single
high-performance uplink channel that can be used to provide up to 600-Mbit/s switch-to-switch connections.
The TNETX3270 incorporates an internal content-addressable memory (CAM) capable of supporting 2,048 end
stations from a single switch. In addition, the device supports 32 user-configurable VLAN-broadcast domains
(IEEE Std 802.1Q), which allows IEEE Std 802.1P priority support interoperability, IEEE Std 802.3X full-duplex
flow control, and a collision-based flow-control scheme. The TNETX3270 also integrates an EEPROM interface
that allows the device to be initialized and configured without the added expense of a CPU. All of these features
on chip greatly reduce the number of external components required to build a switch.
The internal address-lookup engine (IALE) supports up to 2K unicast/multicast and broadcast addresses and
up to 32 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or
non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support
VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown
source- and destination-address packets to ports specified via programmable masks.
TNETX3270
ThunderSWITCH
TM
24/3 ETHERNET
TM
SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B NOVEMBER 1997 REVISED APRIL 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SDRAM Interface
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM-Type and Quantity Indication
38
. . . . . . . . . . . . . . . . .
Initialization
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Refresh
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Routing
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLAN Support
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE Std 802.1Q Headers Reception
40
. . . . . . . . . . . . . . . .
IEEE Std 802.1Q Headers Transmission
40
. . . . . . . . . . . . .
Address Maintenance
40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spanning-Tree Support
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aging Algorithms
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame-Routing Determination
41
. . . . . . . . . . . . . . . . . . . . . . . .
Port Mirroring
44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Trunking/Load Sharing
45
. . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Control
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision-Based Flow Control
46
. . . . . . . . . . . . . . . . . . . . . . . . .
IEEE Std 802.3 Flow Control
46
. . . . . . . . . . . . . . . . . . . . . . . . .
Internal Wrap Test
48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duplex Wrap Test
49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Mirroring
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Copy to Uplink
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions
51
. . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information
52
. . . . . . . . . . . . . . . . . . . . . .
Test Measurement
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-Mbit/s Interface (Ports 0023)
53
. . . . . . . . . . . . . . . . . . . . . . . . . .
10-/100-Mbit/s MAC Interface
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM Interface
56
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIO/DMA Interface
58
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial MII Management Interface
60
. . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Interface
61
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Interface
62
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up OSCIN and RESET
63
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data
64
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGV Package Terminal Layout
4
. . . . . . . . . . . . . . . . . . . . . . . . . .
TNETX3270 Interface Block Diagram
5
. . . . . . . . . . . . . . . . . . . .
Terminal Functions
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIO Register Groups
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Description
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIO Interface
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving/Transmitting Management Frames
18
. . . . . . . .
State of DIO Signals During Hardware Reset
18
. . . . . . . .
Network Management Port
19
. . . . . . . . . . . . . . . . . . . . . . . .
MII Serial Management Interface (PHY Management)
22
. . .
10-Mbit/s and 10-/100-Mbit/s MAC Interface
22
. . . . . . . . . . . .
Receive Control
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Giant (Long) Frames
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Frames
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Filtering of Frames
23
. . . . . . . . . . . . . . . . . . . . . . .
Data Transmission
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Control
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Performance Optimization
(APO) (Transmit Pacing)
23
. . . . . . . . . . . . . . . . . . . . . . . . .
Interframe Gap Enforcement
23
. . . . . . . . . . . . . . . . . . . . . .
Backoff
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Versus Transmit Priority
24
. . . . . . . . . . . . . . . . . .
Uplink Pretagging
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Interface
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interaction of EEPROM Load With the SIO Register
28
. .
Summary of EEPROM Load Outcomes
28
. . . . . . . . . . . . .
Compatibility With Future Device Revisions
28
. . . . . . . . .
JTAG Interface
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIGHZ instruction
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Interface
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lamp Test
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-LED Display
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Configurations
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-Mbit/s MAC Interfaces (Ports 0023)
30
. . . . . . . . . . . . . . .
10-/100-Mbit/s MAC Interfaces (Ports 2426)
34
. . . . . . . . . . .
10-/100-Mbit/s Port Configuration
34
. . . . . . . . . . . . . . . . . .
10-/100-Mbit/s Port Configuration
in a Nonmanaged Switch
35
. . . . . . . . . . . . . . . . . . . . . . . . .
10-/100-Mbit/s Port Configuration
in a Managed Switch
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
TNETX3270
ThunderSWITCH
TM
24/3 ETHERNET
TM
SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B NOVEMBER 1997 REVISED APRIL 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
V
DD(2.5V)
GND
GND
GND
DD(3.3V)
V
PGV PACKAGE
(TOP VIEW)
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
DD26
DD27
DD28
V
DD(2.5V)
DD29
DD30
DD31
GND
DCAS
DRAS
DW
V
DD(3.3V)
DCLK
GND
DA00
DA01
V
DD(2.5V)
DA02
DA03
DA04
GND
DA05
DA06
DA07
DA08
DA09
DA10
GND
DA11
DA12
V
DD(2.5V)
DA13
TH0RENEG
GND
TH0TXD0
TH0TXD1
TH0TXD2
TH0TXD3
TH0TXEN
GND
TH0SYNC
TH0CLK
TH0COL
TH0CRS
V
DD(2.5V)
TH0RXDV
TH0RXD0
TH0RXD1
V
DD(3.3V)
TH0RXD2
TH0RXD3
TH0LINK
TH1RENEG
TH1TXD0
GND
TH1TXD1
TH1TXD2
V
DD(2.5V)
TH1TXD3
TH1TXEN
MDIO
MRESET
V
DD(2.5V)
ECLK
EDIO
RESET
LEDDATA
LEDCLK
OSCIN
TRST
TDI
V
DD(3.3V)
TDO
TMS
TCLK
V
DD(2.5V)
M26FORCE10
M26FORCEHD
M26LINK
M26RXER
GND
M26RXDV
M26RXD3
M26RXD2
M26RXD1
M26RXD0
GND
M26RCLK
M26CRS
V
DD(2.5V)
M26COL
M26TXER
GND
M26TXEN
M26TXD3
M26TXD2
M26TXD1
M26TXD0
M26TCLK
GND
M25FORCE10
M25FORCEHD
M25LINK
V
DD(2.5V)
M25RXER
M25RXDV
GND
M25RXD3
V
DD(3.3V)
M25RXD2
M25RXD1
M25RXD0
GND
M25RCLK
M25CRS
M25COL
V
DD(2.5V)
M25TXER
M25TXEN
M25TXD3
1
5
10
15
20
25
35
40
45
50
55
60
180
175
170
165
160
155
150
145
140
135
130
125
121
DD25
DD24
V
DD23
DD22
GND
DD21
DD19
DD18
DD17
DD16
DD15
DD14
DD12
DD1
1
DD10
DD09
DD08
DD07
DD06
DD05
DD04
DD03
DD02
DD01
DD00
SRXRDY
STXRDY
SAD1
SAD0
SINT
SRDY
SCS
SDA
T
A
7
SDA
T
A
6
SDA
T
A
5
SDA
T
A
4
SDA
T
A
3
SDA
T
A
2
SDA
T
A
1
SDA
T
A
0
SRNW
SDMA
MDCLK
TH1SYNC
TH1CLK
TH1COL
DD(2.5V)
TH1CRS
TH1RXDV
TH1RXD0
TH1RXD1
TH1RXD2
TH1RXD3
TH1LINK
TH2RENEG
TH2TXD0
TH2TXD1
TH2TXD2
TH2TXD3
TH2TXEN
TH2SYNC
TH2CLK
TH2CRS
TH2RXDV
TH2RXD0
TH2RXD1
TH2RXD2
TH2RXD3
M24TXD0
M24TXD1
M24TXD2
M24TXD3
M24TXEN
M24TXER
M24COL
M24CRS
M24RCLK
M24RXD0
M24RXD1
M24RXD2
M24RXD3
M24RXDV
M24RXER
M24LINK
M
24FORCEHD
M24FORCE10
M25TCLK
M25TXD0
M25TXD1
M25TXD2
V
GND
TH2COL
DD(2.5V)
DD20
V
DD(3.3V)
GND
DD(2.5V)
V
DD(2.5V)
V
DD(2.5V)
V
DD(2.5V)
V
DD13
V
DD(2.5V)
V
DD(2.5V)
V
DD(2.5V)
GND
GND
GND
GND
GND
GND
V
DD(3.3V)
V
DD(3.3V)
V
DD(3.3V)
TH2LINK
M24TCLK
2
3
4
6
7
8
9
11
12
13 14
16
17
18
19
21
22
23 24
26
27
28
29
30
31 32
33
34
36
37
38
39
41
42
43
44
46
47
48
49
51
52
53
54
56
57
58
59
179
178
177
176
174
173
172
171
169 168
167
166
164
163
162
161
159
158
157
156
154
153
152
151
149
148
147
146
144 143
142
141
139
138
137
136
134
133
132
131
129
128
127
126
124
123
122
TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS
AND 3 10-/100-MBIT/S PORTS
SPWS043B NOVEMBER 1997 REVISED
APRIL
1999
TMTM
POST
OFFICE BOX 655303 DALLAS,
TEXAS
75265
5
DA12DA0
MRESET
ECLK
EDIO
DD31DD0
DCLK
DRAS
DCAS
DW
LEDDATA
LEDCLK
SDATA7SDATA0
SAD1SAD0
SRNW
SCS
SRDY
DRAM
Port
LED
Activity
Port
CPU
Interface
Serial
MII
Interface
TH0CLK
TRST
TMS
TCLK
TDI
TDO
TAP
Address
Compare
Statistics
Storage
MIB
JTAG
Test Access
Port (TAP)
EEPROM
Port
TH0TXD3TH0TXD0
TH0TXEN
TH0COL
TH0CRS
TH0SYNC
TH0RXD3TH0RXD0
TH0RXDV
TH0LINK
MxxTCLK
MxxTXD3MxxTXD0
MxxTXEN
MxxTXER
MxxCOL
MxxCRS
MxxRCLK
MxxRXD3MxxRXD0
MxxRXDV
Three Ports
(2426)
10/100 Mbit/s
MxxRXER
MxxFORCE10
MxxFORCEHD
MxxLINK
MDCLK
MDIO
Network
Statistics
Logic
xx is the port number that is being monitored.
Data Path
LED
Interface
TH0RENEG
TH1CLK
TH1TXD3TH1TXD0
TH1TXEN
TH1COL
TH1CRS
TH1SYNC
TH1RXD3TH1RXD0
TH1RXDV
TH1LINK
TH1RENEG
TH2CLK
TH2TXD3TH2TXD0
TH2TXEN
TH2COL
TH2CRS
TH2SYNC
TH2RXD3TH2RXD0
TH2RXDV
TH2LINK
TH2RENEG
CPU
Interface
SDRAM
Controller
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
MUX
MUX
MUX
Controller (MAC)
Controller (MAC)
MII
MII
MII
Eight Ports
(1623)
10 Mbit/s
Eight Ports
(0815)
10 Mbit/s
Eight Ports
(0007)
10 Mbit/s
Queue
Manager
EEPROM
Interface
SDMA
SINT
STXRDY
SRXRDY
Miscellaneous
Functions
OSCIN
RESET
MII
Figure 1. TNETX3270 Interface Block Diagram
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