TPS2140, TPS2141
TPS2150, TPS2151

SLVS399 JANUARY 2002

ADJUSTABLE LDO AND SWITCH WITH DUAL CURRENT LIMIT FOR

USB HIGH-POWER PERIPHERAL POWER MANAGEMENT

www.ti.com

FEATURES

Complete Power Management Solution for
USB High-Power Peripherals

250 mA Low-Dropout Regulator (LDO) With
Enable and 325 mA (Typ) Current Limit

LDO Supports 2.7 V to 5.5 V V

and 0.9 V to

3.3 V Adjustable V

OUT

40 m

(Typ) High-Side MOSFET With Dual

Current Limit

Undervoltage Lockout and Power Good for
LDO and Switch

CMOS- and TTL-Compatible Enable Inputs

A (Typ) Supply Current

A (Typ) Standby Supply Current

Available in 14-Pin HTSSOP (PowerPAD

)

40

C to 85

C Ambient Temperature Range

Alternative to TPS2148/58 3.3-V LDO With
3.3-V Switch and 5-V Switch

APPLICATIONS

High-Power USB

Peripherals

ADSL Modems
Digital Still and PC Cameras
Zip Drives
Speakers

DSP Sequencing

DESCRIPTION

The TPS2140/41/50/51 is a USB 1.0 and 2.0
Specification-compatible IC containing a dual-current-
limiting power switch and an adjustable low dropout
regulator (LDO). Both the switch and LDO limit inrush
current by controlling the turnon slew rate. The unique
dual-current-limiting feature of the switch allows USB
peripherals to utilize high-value capacitance at the
output of the switch, while keeping the inrush current
low. During turnon, the switch limits the current
delivered to the capacitive load to less than 100 mA.
When the output voltage from the switch reaches about
93% of the input voltage, the switch power good output
goes high, and the switch current limit increases to
800mA (minimum), at which point higher current loads
can be turned on. The higher current limit provides short
circuit protection while allowing the peripheral to draw
maximum current from the USB bus.

The switch and LDO function independently, providing
flexibility in DSP applications requiring separate core
and I/O voltages. For example, in a DSP application
operating from a 3.3-V rail, the LDO can supply the DSP
core voltage down to 0.9 V, while the switch powers the
3.3-V (typical) DSP I/O supply. If supply sequencing is
required, the LDO power good output can be used to
enable the switch.

AVAILABLE OPTIONS

TARGET

PACKAGE

PACKAGED DEVICES

DESCRIPTION

TARGET

APPLICATION

PACKAGE

AND PIN

COUNT

ACTIVE LOW

(SWITCH)

ACTIVE HIGH

(SWITCH)

C to 85

Adjustable LDO and 3.3 V switch with dual current
limit

DSP

HTSSOP-14

TPS2140IPWP

TPS2150IPWP

C to 85

Adjustable LDO and 5 V switch with dual current
limit

USB

HTSSOP-14

TPS2141IPWP

TPS2151IPWP

NOTE: All options available taped and reeled. Add an R suffix (e.g., TPS2140IPWPR)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

2002, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.
USB is a trademark of Universal Serial Bus Association.

TPS2140, TPS2141
TPS2150, TPS2151

SLVS399 JANUARY 2002

www.ti.com

functional block diagram

2-Level

Current

Limit

Driver

SW_OUT

VREF

VCC

Select

Charge

Pump

Thermal

Sense

0.9 V to 3.3 V

250 mA

LDO

SW_IN

LDO_IN

SW_EN

LDO_EN

GND

SW_OUT

SW_PG

SW_PLDN

LDO_PG

ADJ

LDO_OUT

LDO_PLDN

The pin is active low for TPS2140 and TPS2141, with an internal pullup.

The pin is active high for TPS2150 and TPS2151, with an internal pulldown.

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ADJ

Feedback adjustment of LDO regulator to set output voltage

GND

Ground

LDO_EN

Enable signal for LDO regulator, active high, no internal pullup or pulldown

LDO_IN

Input of LDO regulator

LDO_OUT

Output of LDO regulator

LDO_PG

Power good signal for LDO output, open-drain, active high

LDO_PLDN

Output pulldown pin used for LDO when connected to LDO_OUT

SW_EN or
SW_EN

Active-high enable for switch on TPS2150 and TPS2151 devices with internal pulldown
Active-low enable for switch on TPS2140 and TPS2141 devices with internal pullup

SW_IN

2, 3

Input of the switch

SW_OUT

12, 13

Output of switch

SW_PG

Power good signal for switch output, active high logic-level signal, no external pullup required.

SW_PLDN

Output pulldown pin used for switch when connected to SW_OUT.

TPS2140, TPS2141
TPS2150, TPS2151

SLVS399 JANUARY 2002

www.ti.com

detailed description

GND

Ground

SW_IN

SW_IN is the input to an integrated N-channel MOSFET, which has a maximum on-state resistance of 65 m

Configured as a high-side switch, the power switch prevents current, flow from OUT to IN and IN to OUT when
disabled. The power switch is rated at 500 mA, continuous current and has a dual current limit feature.

dual current limit

The current limiter for the switch limits the initial current drawn from SW_IN to 100 mA maximum. The user can
estimate the amount of time it takes to charge a capacitor (CL) connected to SW_OUT by using the following
relationship:

I(SW_IN)

/ 0.1 < t

CHG

< CL

I(SW_IN)

/ 0.05

Capacitance in farads. If V

I(SW_IN)

= 5 V, then

CL< t

CHG

<100

When the voltage at output SW_OUT rises above 93% of the voltage at SW_IN, the current limit is increased
to 1800 mA maximum. The SW_PG can be used to turn on loads which may draw more than 50 mA.

In the event of an overload on SW_OUT, the protection circuit limits the current delivered to 1800 mA maximum.
As the output voltage drops and it crosses 80% of the SW_IN voltage, the current limiter reverts back to the
low-current limit mode of 100 mA maximum.

SW_IN also serves as one of the two inputs to an internal voltage selector that provides operating voltage to
the whole device. The other input to the selector is LDO_IN.

SW_OUT

SW_OUT is the output of the internal power-distribution switch.

SW_EN or SW_EN

The logic input disables or enables the power switch. This signal is active low (SW_EN) for TPS2140/41 and
active high (SW_EN) for TPS2150/51. SW_EN has an internal pullup and SW_EN has an internal pulldown.

SW_PG

SW_PG signals the presence of an undervoltage condition on SW_OUT. The pin is driven by a CMOS output
buffer and is pulled low during an undervoltage condition. To minimize erroneous SW_PG responses from
transients on the voltage rail, the voltage sense circuit incorporates a rising and falling edge deglitch filter. When
SW_OUT voltage is lower than 88% of 3.3 V for TPS2140/50, or 5 V for TPS2141/51, SW_PG goes low to
indicate an undervoltage condition on SW_OUT.

SW_PLDN

SW_PLDN is an open drain output incorporated to provide a discharge path. When the power switch is on, this
pin is open; otherwise it is pulled down to ground. When this pin is connected to SW_OUT, the output voltage
fall time is reduced but the rise time remains unaffected.

LDO_IN

The LDO_IN serves as the input to the internal LDO. The adjustable LDO has a dropout voltage of 0.5 V
maximum and is rated for 250 mA of continuous current. LDO_IN is also used as one of the two inputs for V

selection.

TPS2140, TPS2141
TPS2150, TPS2151

SLVS399 JANUARY 2002

www.ti.com

detailed description (continued)

LDO_OUT

LDO_OUT is the output of the internal LDO. It has an output voltage range of 0.9 V to 3.3 V.

LDO_EN

LDO_EN is used to enable or disable the internal LDO and is compatible with CMOS and TTL logic. LDO_EN
is an active high input.

ADJ

ADJ is used to adjust the LDO output voltage (LDO_OUT) anywhere between 0.9 V and 3.3 V by connecting
a resistor divider from LDO_OUT to ground (ADJ connects to the center point of the resistor divider).

LDO_PG

LDO_PG signals the presence of an undervoltage condition on LDO_OUT. LDO_PG is an open-drain output
and is pulled low during an undervoltage condition. To minimize erroneous LDO_PG responses from transients
on the voltage rail, the voltage sense circuit incorporates a 150-

s falling deglitch filter. When the LDO_OUT

voltage is lower than 94% of a threshold voltage (set by an external resistor divider), LDO_PG goes low to
indicate an undervoltage condition. A pullup resistor from LDO_PG to a power rail is required for proper
operation.

LDO_PLDN

LDO_PLDN is an open drain output incorporated to provide a discharge path. When the LDO is on, this pin is
open; otherwise, it is pulled down to ground. When this pin is connected to LDO_OUT, the output voltage fall
time is reduced but the rise time remains unaffected.

current sense

Both the power switch and the LDO have integrated current sense circuits. When an overload or short circuit
is encountered, the current-sense circuitry sends a control signal to the driver. The driver reduces the gate
voltage until the current drops back to the limiting value.

thermal sense

A dual-threshold thermal trip is implemented to protect the device. The lower thermal trip point is used to protect
the device during an overcurrent condition. The higher thermal trip point is used to protect the device when the
junction temperature rises but not due to an overcurrent condition.

undervoltage lockout

A voltage sense circuit monitors both input voltages on SW_IN and LDO_IN. When the input voltage is below
its respective threshold, a control signal turns off the related channel (the power switch or the LDO).

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TPS2141

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TPS2141