VIA Technologies, Inc.

Preliminary VT6516 Datasheet

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VIA Technologies, Inc.

Preliminary VT6516 Datasheet

ABLE OF

ONTENTS

ABLE OF

ONTENTS

................................................................................................................................ 3

IGURES AND

ABLES

............................................................................................................................... 4

EVERSION

ISTORY

................................................................................................................................ 5

EATURES

................................................................................................................................................ 6

LOCK

IAGRAM

...................................................................................................................................... 9

ALL OUT

IAGRAM

............................................................................................................................... 11

RMII-mode Ball out Diagram ........................................................................................................... 11
MII-mode Ballout Diagram............................................................................................................... 12

OGIC

YMBOL

...................................................................................................................................... 13

ESCRIPTIONS

.................................................................................................................................. 14

UMPER

TRAPPING

................................................................................................................................. 18

SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 19

1. G

ENERAL

ESCRIPTION

...................................................................................................................... 19

2. T

VIA E

THER

WITCH

RCHITECTURE

............................................................................................ 19

2.1 Switch initialization procedures .................................................................................................. 19
2.2 Packet receiving and forwarding follow .......................................¿ ù

» ~

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Å Ò

¡ C

3. I

NTERFACE

ESCRIPTIONS

................................................................................................................... 20

3.1 Buffer Memory (SDRAM) Interface and Table (SRAM) interface..¿ ù

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4. F

UNCTIONAL

ESCRIPTION

................................................................................................................. 33

4.1 Packet Reception and Address recognition.................................................................................. 33
4.2 Packet Forwarding and VLAN..................................................................................................... 33
4.3 Network Management Features................................................................................................... 34

SECTION II REGISTER MAP............................................................................................................... 36

1. R

EGISTER

ABLES

............................................................................................................................. 36

2 CPU I

NTERFACE

EGISTERS

......................................................................................................... 36

3 S

WITCH

NTERNAL

EGISTERS

..................................................................................................... 37

4. D

ETAIL OF

WITCH

EGISTER

.............................................................................................................. 44

4.1 Registers of SDRAM Control Module......................................................................................... 44
4.2 Registers of SRAM Control Module............................................................................................ 46
4.4 Registers of Buffer Control Module............................................................................................. 48
4.5 Registers of Forwarding Control Module ................................................................................... 49
4.6 Registers of PHY Control Module .............................................................................................. 53
4.7 Registers of EEPROM Control Module ....................................................................................... 55
4.8 Registers of CPU Interface Module............................................................................................. 56
4.9 Registers of MAC/IO Control Module ......................................................................................... 59
4.10 Registers of CPU IO Control Module....................................................................................... 63

SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 65

BSOLUTE

AXIMUM

ATINGS

............................................................................................................... 65

DC C

HARACTERISTICS

............................................................................................................................ 65

AC C

HARACTERISTICS

............................................................................................................................ 65

ACKAGE

ECHANICAL

PECIFICATIONS

................................................................................................. 73

VIA Technologies, Inc.

Preliminary VT6516 Datasheet

IGURES AND

ABLES

Figure 1: Block Diagram .............................................................................................9
Figure 3-3 .................................................................................................................22
Figure 3-6: Algorithm of Initialization of Free Link Lists. ..........................................22
Figure 3-1 SRAM......................................................................................................26
Figure 3-2 Free buffer link structure ..........................................................................27
Table 1-0 Free buffer link structure............................................................................27
Figure 3-5 The Address table entries structure +........................................................27
Table 1-1 Address table structure ..............................................................................28
Table 3-1 RMII interface signals................................................................................30
Figure 3-1 RMII timing diagram ................................................................................30
Table 3-2 MII interface signals ..................................................................................31
Figure 3-2 MII timing diagram ..................................................................................31

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