VIA Technologies, Inc.

Preliminary VT86C100A

RELIMINARY

ELEASE

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Copyright Notice:

1995, Via Technologies Incorporated. Printed in Taiwan. A

IGHTS

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Preliminary VT86C100A

VT86C100A PCI F

AST

THERNET

ONTROLLER

EATURES

* Single chip Fast Ethernet controller for PCI bus interface

compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system- ID

Provides a direct connection to PCI bus

Supports two network ports : 10/100 M MII interface

* High performance PCI mastering structure
-- VIA self-define 128 bytes memory I/O or register I/O based command and status register

Software oriented chain structure description to minimize hardware complexity

-- Include on chip bus master DMA with programmable burst length for low CPU utilization
-- Dynamic transmit packet auto queuing for back auto queuing for bac for back to back transmissin
-- Programmable activity polling intervals for description DMA
-- Programmable DMA arbitration priority to minimize overflow under flow condition
-- Support early receive and early transmit interrupt for software parallel processing
-- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time
* Provides standard 100-M bits MII interface

Support 100Base-TX with CAT5 UTP, STP and fiber cables

-- Support 100Base-T4 with CAT3, CAT4, CAT 5 UTP, STP

* 10/100Mhz full duplex, half duplex operation
* Contains two deeper 2K bytes FIFO for receive and transmit controller both supports bursts of

up to full Ethernet length

Programmable receive and transmit FIFO threshold control for optimize PCI throughput

* Flexible dynamically load EEPROM algorithm.

Load after power-up

Dynamic auto reload

Embedded programming for configure modification

Dynamic direct programming for manufacturing

* Support physical, Broadcast, Multicast address filtering using hashing function
* Support Magic packet and wake on address filtering
* Support external Bootrom up to 64K bytes no external address latch
* Software controllable power down feature
* Single +5V supply, 0.5um standard CMOS technology
* 128 pin PQFP package

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Preliminary VT86C100A

ESCRIPTIONS

No.

Name

Type

Description

PCI Bus Interface

121-

124,127-

128,1-

2,5,7-

9,11-

14,27-
32,35-

36,38,39-

40,42-46

AD31-0

I/O

Address/Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases. The
address phase is the clock cycle in which FRAME# is asserted. Write
data is stable and valid when IRDYB is asserted and read data is stable
and valid when TRDYB is asserted.

115

PCICLK

PCICLK provides timing for all transactions on PCI and is an input pin
to every PCI device.

113

INTA#

INTA# is an asynchronous signal which is used to request an interrupt

114

PCIRST#

When PCIRST# is asserted low, the VT86C100A chip performs an
internal system hardware reset. PCIRST# may be asynchronous to CLK
when asserted or deasserted. It is recommended that the deassertion be
synchronous to guarantee clean and bounce free edge.

3,16,26,37

CBE#[3:0]

Bus Command/Byte Enables are multiplexed on the same PCI pins.
During the address phase of a transaction, CBE3-0B define the Bus
Command. Burring the data phase, CBE3-0B are used as Byte Enables.
The Byte Enables define which physical byte lanes carry meaningful
data. CBE0B applies to byte 0 and CBE3B applies to byte 3.

IDSEL

Used as a chip select during PCI configuration cycle.

FRAME#

I/O

Cycle Frame is driven by the current master to indicate the beginning
and duration of an access. FRAME# is asserted to indicate a bus
transaction is beginning. While FRAME# is asserted, data transfers
continue. When FRAME# is deasserted, the transaction is in the final
data phase.

IRDY#

I/O

Initiator Ready indicates the initiating agent's ability to complete the
current data phase of the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a write, IRDY# indicates that valid data is
present on AD31-0. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.

TRDY#

I/O

Target Ready indicates the target's agent's ability to complete the current
data phase of the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a read, TRDY# indicates that valid data is
present on AD31-0. During a write, it indicates the target is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.

DEVSEL#

I/O

Device Select, when actively driven, indicates the driving device has
decoded its address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been selected.

STOP#

I/O

VT86C100A drives STOP# to disconnect further traction.

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Preliminary VT86C100A

PAR

T/S

Parity is even parity across AD31-0 and CBE3-0B. PAR is stable and
valid one clock after the address phase. For data phases PAR is stable
and valid one clock after either IRDY# is asserted on a write transaction
or TRDY# is asserted on a read transaction.

118

GNT#

Bus grant asserts to indicate to the VT86C100A that access to the bus is
granted.

119

REQ#

Bus request is asserted by the bus master indicate to the bus arbiter that
it wants to use the bus.

PERR#

I/O

Parity error asserts when a data parity error is detected

120

PME#

Power management event interrupt

111

HDRST

When PCIRST# is asserted low, the VT86C100A chip performs an
internal system hardware reset. Then HDRST is asserted high for
external device reset signal like PHY device.

Network Interface

MCOL

Collision detect when the external PHY device

MCRS

Carrier sense is asserted by the external PHY when the media is active

92-95

MTXD[3-0]

MII 4 parallel transmit data lines. This data be synchronized to assertion

by the MTXC signal

MTXEN

Transmit enable signals that the transmit is active in the MII port to an

external PHY device

MTXC

MII transmit clock supports the 25mhz or 2.5mhz transmit clock

supplied by the external PMD device. This clock should always be
active.

100

MERR

MII receive error asserts when a data decoding error is detected by

external PHY device.

101

MRXC

MII receive clock supports the 25mhz or 2.5mhz clock. This clock is

recovered by the PHY.

102

MRXDV

MII data valid

103-106

MRXD[0-3]

Four parallel receive data lines. This data be driven from external PHY

be synchronized with MRXC signal.

109

MDC

MII management data clock be soured by VT86C100A MDC bit

(MIIR:0) to the external PHY devices as timing reference for the
MDIO signal.

110

MDIO

I/O

MII management data input/output, read from MDI bit (MIIR:1) or

written from MDO bit (MIIR:2)

112

GPIO

I/O

GPIO

External Memory Support & General purpose I/O support

EECS

EEPROM Chip Select: Chip select signal for the external EEPROM

when a EEPROM is used to provide the configuration data and
Ethernet Address. A 100K pull-up resistor is connected.

BPRD#

Boot PROM Read: Read the Boot ROM on the memory support data

bus.

MD0/

EEDO

I/O

Bootrom data 0
Serial ROM Data output

MD1/

EEDI

O/O

Bootrom data 1
Serial ROM Data input

MD2/ EECLK

O/O

Bootrom data 2
Serial ROM Clock signal

54-55,58-

MD3-7

I/O

Bootrom Data [3-7] :

VIA Technologies, Inc.

Preliminary VT86C100A

UNCTIONAL

ESCRIPTIONS

1. G

ENERAL

ESCRIPTION

The VT86C100A Rhine ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for
easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include:
twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and
Early Interrupt Receive/Transmit.

The VT86C100A integrates the entire bus interface of PCI systems. Setting hardware jumpers or software
configures the VT86C100A bus interface. The VT86C100A also complies with PCI specification v2.1.. The
VT86C100A supports the Media Independent Interface (MII) network interface.

1.1 FIFO A

ONTROL

OGIC

The VT86C100A incorporates two independent 2K bytes deeper FIFO for transmit or receive data from
system interface or to the network interface, providing temporary storage of data, free host system from the
real-time demands on network.
The VT86C100A enhanced the FIFO management logic to handle received data packets up to four packets
before transfer to system data buffer. This ability reduce the packets losing due to PCI bus mastering abrition
latency.

2. N

ETWORK

NTERFACE

The VT86C100A Rhine ACPI support one MII interface

2.1 MII Interface

The MII interface is an IEEE 802.3 compliant interface that provides a simple and easy interconnection
between the MAC layer and PHY device. This interface has support the following characteristics :

Support both 10M and 100M data rate.

Contains data and synchronous clock

4-bit independent receive and transmit data.

Uses TTL signal levels and compatibles with common CMOS processes.

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Preliminary VT86C100A

EEPROM Interface and Programming

VT86C100A uses an 93C46 to store configuration data and Ethernet address.

.1. EEPROM Contents

D15

3FH

Reserved for 93C46

10H

0FH

73H

0EH

CFG_D

CFG_C

0DH

CFG_B

CFG_A

0CH

BCR1

BCR0

0BH

MAX_LAT

MIN_GNT

0AH

Reserved

09H

KEY5

08H

KEY3

KEY2

07H

KEY1

KEY0

06H

Reserved

05H

SUBVID1

SUBVID0

04H

SUBSID1

SUBSID0

03H

Reserved

02H

Ethernet Address 5

Ethernet Address 4

01H

Ethernet Address 3

Ethernet Address 2

00H

Ethernet Address 1

Ethernet Address 0

Note 1. The word on location 03H is optional to user's application requirement.
Note 2. Programming 73H into the upper address is required to protect the Ethernet address from being destroyed accidentally
Note 3. The word on location 04H, 05H is sub-System ID, sub-Vendor ID in PCI specification 2.1.

3.2. D

IRECT

ROGRAMMING OF

EEPROM

The VT86C100A features a easy way to program external EEPROM in-situ. When the RESET is active and if
the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current
EEPROM has not been programmed yet. This will allow the VT86C100A to enter Direct Programming mode
if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to
the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and
DI(MD1) outputs respectively. These outputs will be latched so the user can generate a clock on SK by
repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals as per
the 93C46 data sheet.

To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as
described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data
Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the

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Preliminary VT86C100A

EEPROM has been programmed and verified (remember to program the upper byte of 0EH & 0FH with
73H), the user must give VT86C100A a power-on reset to return to normal operation and to read in the new
data.

The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the
upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is no
way to change the contents of EEPROM except Configuration Registers A, B, and C, which will be discussed
in the following paragraph. For more information, refer to EECSR.

3.3. E

MBEDDED

ROGRAMMING OF

EEPROM

If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C100A is loading the
EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct
Programming mode. However, the user can still program the configuration registers A, B, and C using the
Embedded Programming mode by following the routine specified in the pseudo code below. This operation
will work regardless of the value of EECONFIG. The setting of the EELOAD bit of Configuration Register B
starts the EEPROM write process. Care should be taken not to accidentally modify the POL and GDLNK bits
because these two bits return the value indifferent from the setting. This programming process is ended when
the EELOAD bit goes to zero.

EEPROM_EMB_PROG ( )

// defined constant:

CONFIG_B, EELOAD

// declared register: value, config_for_A, config_for_B, config_for_C
// declared function: DISABLE_INTERRUPTS, ENABLE_INTERRUPTS, READ, WRITE, WAIT
DISABLE_INTERRUPTS ( );
value = READ (

CONFIG_B);

value = value |

EELOAD;

WRITE (

CONFIG_B, value);

READ (

CONFIG_B);

WRITE (

CONFIG_B, config_for_A);

WRITE (

CONFIG_B, config_for_B);

WRITE (

CONFIG_B, config_for_C);

while (value ||

EELOAD)

{

value = READ (

CONFIG_B);

WAIT ( );

}
ENABLE_INTERRUPTS ( );

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Preliminary VT86C100A

4. PCI Configuration Space

Device ID

( 6100 )

Vendor ID

( 1106 )

00 h

STATUS

(DEVS1, DEVS0 ) = ( 1 , 0 )

COMMAND

( MMSPACE, IOSPACE)

04 h

CLASS CODE

( 02_00_00 )

Revision ID

( 04 )

08 h

BIST

( 00 )

Header type

( 00 )

Latency Timer

( R/W )

Cache Line

( R/W )

0c h

CSR Memory Map Base Addr 000

0 0 1

10 h

CSR IO MAP SPACE 000

0 0 0

14 h

Sub-System ID

Sub-Vendor ID

2c h

EXP ROM BASE [ 31: 15 ]

ROM14

0000_0000_00000

30 h

Reserved

Max_LAT
( 00 )

Min_GNT
( 00 )

INT PIN
( 01 )

INTLINE

INTL [7:0]

3c h

Reserved

MODE3

MODE2

FIFOTST

MODE0

50H

5. M

AGIC

ILTERING AND

AKE ON

AGIC

The VT86C100A provides an one level power down mode. The BIOS or Network OS device driver can

configure Register A to diagnostic mode then set the Power-on bit of the diagnostic port to "on." When the
VT86C100A is in Power down mode, all power to the PCI interface is cut off and the chip clock is stopped.
Other registers are read only. Only the diagnostic port is read/writeable.
The VT86C100A can store one "Magic Key" (6 bytes Ethernet address) as external trigger event. When
VT86C100A received one Magic Key address packet, the PME# or GPIO1 will be generated to system.
These signal can be asserted to ATX power PS-ON (refere to ATX specification v2.01) or mother board wake
up interrupt line like ring-in.

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Preliminary VT86C100A

6. B

UFFER

ANAGEMENT

& H

OST

OMMUNICATION

The VT86C100A provides an simply and effective buffer management and host communication

method through the PCI Bus mastering : There are two descriptor lists, one for receive and one for transmit.
The base of these two list are pointed into the CRDA (18h) and CTDA (1ch) registers.

The descriptor list reside in the host physical memory address space with double word boundary.

And each descriptor lists just point to one single buffer, but a data buffer consists of either an entire frame or
part of a frame. Data chain can be enabled or disabled by DES1 C bit. Data buffer also reside in host physical
memory double word boundary space.

The device driver can make the last descriptors next link be point to first descriptor address, become

a ring buffer structure.

Descriptor 0

Buffer 1

Descriptor 1

Buffer 1

Next Descriptor

Figure 6-1 VT86C100A Buffer Management : Chain buffer Structure

6.1 D

ESCRIPTOR

ING AND

HAIN

TRUCTURE

6.1.1 R

ECEIVE

ESCRIPTORS

Figure 6-2 shows the receive descriptor format :
Providing single buffer, one byte-count buffers, and next descriptor address. And Chain bit control

span multiple data buffers data chain to be compatible various types of memory management schemes..

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Preliminary VT86C100A

RDES0

0 0 0 0

FLNG[10:0]

RSR1

RSR0

RDES1

Reserve

0000

RLNG[10:0]

RDES2

Rx Data Buffer Start Address

RDES3

Next Descriptor Address

IGURE

6-2

THE RECEIVE DESCRIPTOR FORMAT

6.1.2. R

ECEIVE

ESCRIPTOR

0 (RDES0)

RDES0 contain the received frame status, the frame length and the descriptor ownership information.

Owner : This bit control by driver, 1 to identify this descriptor own by
VT86C100A controller, 0 means this descriptor be a free descriptor; Driver must
set this bit be zero when initialed.
Extend Frame Length : Extend byte count for no-normal size Ethernet frame
Frame Length : Received frame length,

Received OK : The VT86C100A received a good packet from network.
Multicast Address Received : VT86C100A MAC received multicast address
packet
Boardcast Address Received : VT86C100A MAC received boardcast address
packet
Physical Address Received : Physical address received
CHAIN : means of chain buffer,
Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer
descriptor, or chained buffer structure be follows :
STP EDP Description
1 1 Single buffer descriptor
1 0 First buffer descriptor, further buffer chained
0 1 Chained buffer packet end
0 0 X
End of Packet : End of Packet buffer
Receive Status Register 0 :
Buffer Error : Receive Buffer Error
System bus error :
Runt Packet Received :
Long Packet Received :
FIFO Overflow :
Frame Align Error :
CRC Error : received frame CRC checksum error
Receive Error : this bit be set by CRC error or frame alignmnet error or FIFO
overflow or System bus error.

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Preliminary VT86C100A

6.1.3. R

ECEIVE

ESCRIPTOR

1 (RDES1)

RDES1 contain the interrupt control enable, the chained frame identical and the receive buffer

fragment size information.

Interrupt Control : This bit support for interrupt PACEing , set 1 mean the
VT86C100A received this descriptor will generate the interrupt.

Chain : Chain buffer , this bit be set to 1 means there are chained buffer in next
descriptor
Extend Fragment of Frame Length : must be zero now.
Rx buffer Size : Receive buffer size for this descriptor, the total byte count of
whole frame will be stored in last descriptors

6.2.1. T

RANSMIT

ESCRIPTORS

RDES0

Reserve

TSR1

TSR0

RDES1

Reserve

TCR

0000

TLNG[10:0]

RDES2

Tx Data Buffer Start Address

RDES3

Next Descriptor Address

IGURE

6-3

THE TRANSMIT DESCRIPTOR FORMAT

6.2.2. T

RANSMIT

ESCRIPTOR

0 (TDES0)

DES0 contain the received frame status, the frame length and the descriptor ownership information.

Owner : This bit control by driver, 1 to identify this descriptor own by
VT86C100A controller, 0 means this descriptor be a descriptor waiting for
transmit; Driver must set this bit be zero when initialed.

Transmit Status Register 1
Transmit OK : This bit be 1 for transmission error, the transmit include
following
- internal FIFO under-flow
- excessive collision (ABT)
- late collision (OWC)
- carrier sense lost (CRS)

JAB

Jabber : This bit will set high if Jabber condition happens. Writing to this bit has
no effect
System Error : VT86C100A MAC experience error master abort, target abort,
parity error.

Reserve

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Preliminary VT86C100A

CRS

Carrier Sense lost bit is set when the carrier is lost during the transmission of a packet.

OWC

Late Collisions : This bit is set when late collision occurred.

ABT

Transmit Abort : transmit module abort after excessive collision.

7-0

TSR0

Transmit Status Register 0
CD heartbeat : this bit only effective in 10Base-T mode. When set, this bit
indicates a heartbeat collision check failure.
Collision retry count : this 4-bits counter indicates the number of collisions that
occurred

FIFO under-flow : this bit set indicates that the transmitter aborted by transmit
FIFO encountered an empty while transmitting a frame.
Deferred: When set, indicates that the VT86C100A had to defer while ready to
transmit a frame because carrier was asserted.

6.2.3. T

RANSMIT

ESCRIPTOR

1 (TDES1)

DES1 contain the transmit status, the frame length and the descriptor ownership information.

Transmit Configure Register
Interrupt Control : This bit support for interrupt PACEing , set 1 mean the
VT86C100A received this descriptor will generate the interrupt.
End of Packet : End of Packet buffer
Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer
descriptor, or chained buffer structure be follows :
STP EDP Description
1 1 Single buffer descriptor
1 0 First buffer descriptor, further buffer chained
0 1 Chained buffer packet end
0 0 X

CRC disable : The VT86C100A transmitter will disable generated the CRC
when this set 1.
Chain : Chain buffer
Extend Fragment of Frame Length : must be zero now.
Transmit buffer size : the fragment of frame buffer size

6.3 Buffer Structure and Interrupt Control

data consists of an entire frame or part of a frame, but it cannot exceed a single Ethernet frame size. Buffers

contain only data; All buffer status is maintained in the descriptor . Data chaining can be enable or disable by
Chain bit in DES1[15]. The interrupt control also can be enable or disable by DES1[23]

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Preliminary VT86C100A

VT86C100A R

EGISTERS

Group 1 : Internal Command Status Register (CSR) Layout

byte3

byte2

byte1

byte0

type

PAR3/KEY3

PAR2/KEY2

PAR1/KEY1

PAR0/KEY0

TCR

RCR

PAR5/KEY5

PAR4/KEY4

CR1

CR0

IMR2

IMR0

ISR1

ISR0

MAR3

MAR2

MAR1

MAR0

MAR7

MAR6

MAR5

MAR4

Curr Rx Desc Addr

Curr Tx Desc Addr

Current Rx Desc 0

Current Rx Desc 1

Current Rx Desc 2

Current Rx Desc 3

Next Rx Desc 0

Next Rx Desc 1

Next Rx Desc 2

Next Rx Desc 3

Current Tx Desc 0

Current Tx Desc 1

Current Tx Desc 2

Current Tx Desc 3

Next Tx Desc 0

Next Tx Desc 1

Next Tx Desc 2

Next Tx Desc 3

Current Rx DMA Pointer

Current Tx DMA Pointer

Tally counter test port

BCR1

BCR0

MIISR

PHY ADR

MII DATA REG

MIIADR

MIICR

GPIO

TEST

EECSR

CFGD

CFGC

CFGB

CFGA

Tally counter_CRC

Tally counter_MPA

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Preliminary VT86C100A

Configuration and Diagnostic Registers

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/

Write

EELOAD

JUMPE

MMIOE

MIIOPT

AUTO

OPT

MT10E

MT10EOE

78H

Conf. B

QPKTDIS

TPACE

MRDM

TXARB

RXARB

MWW

AIT

MRWA

LATMEM

79H

Conf. C

RES

BROPT

DLYEN

DTSEL

BTSEL

BPS2

BPS1

BPS0

7AH

Conf. D

GPIOEN

DIAG

MRDL

MAGIC

CRAD

CAP

MBA

BAKOPT

7BH

Note :

The shaded area denoted that those bits are also selective via external jumpers.

All reserved bit must be zero.

No.

Name

Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00H

PAR0

R/W

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

01H

PAR1

R/W

DA15

DA14

DA13

DA12

DA11

DA10

DA9

DA8

02H

PAR2

R/W

DA9

DA10

DA11

DA12

DA13

DA14

DA15

DA16

03H

PAR3

R/W

DA17

DA18

DA19

DA20

DA21

DA22

DA23

DA24

04H

PAR4

R/W

DA25

DA26

DA27

DA28

DA29

DA30

DA31

DA32

05H

PAR5

R/W

DA33

DA34

DA35

DA36

DA37

DA38

DA39

DA40

06H

RCR

R/W

RRFT2

RFT1

RFT0

PROM

SEP

07H

TCR

R/W

RTSF

RTFT1

RTFT0

OFST

LB1

LB0

08H

CR0

R/W

RDMD

TDMD

TXON

RXON

STOP

STRT

INIT

09H

CR1

R/W

SRST

RDMD1

TDMD1

KEYPA

DPOLL

FDX

ETEN

EREN

0AH
0BH
0CH

ISR0

R/W

CNT

TXE

RXE

PTX

PRX

0DH

ISR1

R/W

KEYI

SRCI

ABTI

NBFI

PRAI

OVFI

ETI

ERI

0EH

IMR0

R/W

CNTM

BEM

RUM

TUM

TXEM

RXEM

PTXM

PRXM

0FH

IMR1

R/W

KEYIM

SRCM

ABTM

NBFM

PRAIM

OVFM

ETM

ERM

10H

MAR0

R/W

FB7

FB6

FB5

FB4

FB3

FB2

FB1

FB0

11H

MAR1

R/W

FB15

FB14

FB13

FB12

FB11

FB10

FB9

FB8

12H

MAR2

R/W

FB23

FB22

FB21

FB20

FB19

FB18

FB17

FB16

13H

MAR3

R/W

FB31

FB30

FB29

FB28

FB27

FB26

FB25

FB24

14H

MAR4

R/W

FB39

FB38

FB37

FB36

FB35

FB34

FB33

FB32

15H

MAR5

R/W

FB47

FB46

FB45

FB44

FB43

FB42

FB41

FB40

16H

MAR6

R/W

FB55

FB54

FB53

FB52

FB51

FB50

FB49

FB48

17H

MAR7

R/W

FB63

FB62

FB61

FB60

FB59

FB58

FB57

FB56

18H

RDA0

R/W

AB7

AB6

AB5

AB4

AB3

AB2

AB1

AB0

19H

RDA1

R/W

AB15

AB14

AB13

AB12

AB11

AB10

AB9

AB8

1AH

RDA2

R/W

AB23

AB22

AB21

AB20

AB19

AB18

AB17

AB16

1BH

RDA3

R/W

AB31

AB30

AB29

AB28

AB27

AB26

AB25

AB24

1CH

TDA0

R/W

AB7

AB6

AB5

AB4

AB3

AB2

AB1

AB0

1DH

TDA1

R/W

AB15

AB14

AB13

AB12

AB11

AB10

AB9

AB8

1EH

TDA2

R/W

AB23

AB22

AB21

AB20

AB19

AB18

AB17

AB16

1FH

TDA3

R/W

AB31

AB30

AB29

AB28

AB27

AB26

AB25

AB24

6CH

MPHY

R/W

MPO1

MPO0

PHYAD

PHYAD0

6DH

MIISR

R/W

GPIO1P

LEDPO

MFDC

PHYOP

MIIERR

MRERR

LNKFL

SPEED

6EH

BCR0

R/W

REQOP

CRFT2

CRFT1

CRFT0

DMAL2

DMAL1

DMAL0

VIA Technologies, Inc.

Preliminary VT86C100A

1.1 Configure Register Layout

Configuration Register A (0x78)

GPIO2OE

MD3

GPIO2OE : Output enable of GPIO2 pin
GPIO2O : Output to GPIO2 pin
GPIO2I : GPIO2 input status
AUTOOPT : enable receive event auto transmit descriptor polling

MMIEN : Memory mapped IO enable, accept memory command

GPIO2

JUMPER : Jumper mode to select PHY and operation mode
EELOAD : Enable EEPROM embedded and direct programming

Configuration Register B (0x79)

LATMEN

n/a

LATMEN: Latency timer effect enable
MRWAIT : Master read insert one wait state 2-2-2-2
MWWAIT: Master write insert one wait state 2-2-2-2
RXARBIT : the receiving FIFO DMA will be interleave to transmitting

FIFO DMA after 32 double words transaction.

TXARBIT

n/a

TXARBIT : the transmitting FIFO DMA will be interleave to receiving

FIFO DMA after 32 double words transaction.

MRDM : Memory read multiple capable
TPACEN : Tx descriptor pacing algorithm enable

QPKTDIS

n/a

QPKTDIS : disable transmit frame queuing.

Configuration Register C (0x7A)

Bit

Symbol

Jumper

Function

0-2

BPS0-
BPS3

n/a

Boot PROM Select: Select size at which boot PROM begins and the

size

Bit2

Bit1

Bit0

Size

No Boot PROM

16K

32K

X X

64K

BTSEL : Bootrom timing select

DLYEN : Delay transaction while memory read Bootrom
BROPT : set Bootrom address line above Bootrom size selected to logic

for small size Bootrom

Configuration Register D (0x7B)

BAKOPT

n/a

BAKOPT : Back-off algorithm optional

VIA Technologies, Inc.

Preliminary VT86C100A

VT86C100A Command Status Registers

MAC command and status register Group
CR0:

Command Register 0 (08H; Type=R/W)
This register is used to select register pages, enable or disable remote DMA operation and issue
commands.

Reserved

RDMD

This bit indicates that the VT86C100A receive poll demand enable

TDMD

This bit indicates that the VT86C100A transmit poll demand enable

TXON

This bit indicates that the VT86C100A start transmit state while STRT bit on

RXON

This bit indicates that the VT86C100A start receive state while STRT bit on

STOP

This bit indicates that the VT86C100A into STOP state , this bit set by SFRST bit or
hardware reset

STRT

This bit indicates that VT86C100A enter the start command.

INIT

Initialize Start : When set on the VT86C100A start to set its bus master register the start

CR1:

Command Register 1 (09H; Type=R/W)
This register is used to select register pages, enable or disable remote DMA operation and issue
commands.

This bit is set when VT86C100A enters reset state and is cleared when a start command is
issued to the CR1. It is also set when receive buffer overflows or system error.

6-4

RES

Reserved

DPOLL

Disable transmit auto polling

FDX

This bit set MAC to full duplex in 10BaseT or 100BaseT mode

ETEN

Early transmit mode enable while CFGD[1] be enable, this bit be clear while hardware
reset only

EREN

Early receive mode enable while CFGD[0] be enable, this bit be clear while hardware reset
only

RCR:

Receive Configuration Register (06H; Type=R/W)
This register reflects the NIC receive configuration and reset by hardware reset and software reset

Bit

Symbol

Description

RRSF

Receive store and forward

6-5

RFT[1-0]

Receive FIFO Threshold.
RRFT2 RRFT1 RRFT0 Threshold
0 0 0 64 bytes
0 0 1 32
0 1 0 128
0 1 1 256
1 0 0 512
1 0 1 768
1 1 0 1024
1 1 1 Receive store and forward

PRO

If PRO=1, all packets with physical destination address are accepted. If PRO=0, physical
address must match the node address programmed in PAR0-5

If AB=1, packets with broadcast destination address are accepted. If AM=0, packets with
broadcast destination are rejected.

If AM=1, packets with multicast destination address are accepted. If AM=0, packets with
multicast destination are rejected.

VIA Technologies, Inc.

Preliminary VT86C100A

ISR:

Interrupt Status Register (0CH; Type=R/W)
This register reflects the NIC status. The host reads it to determine the cause of the interrupt
Individual bits are cleared by writing a "1" to the corresponding bit. It must be cleared after
power up.

Magic packet key received interrupt status

Port status change interrupt status

transmit abort interrupt status, this bit will be set while excessive collision

No more receive buffer to use

FIFO overflow condition, next packet race into FIFO with current packet

receiving FIFO overflow interrupt status

Transmit descriptor underflow while in early transmit mode or general I/O pin M10TENI
status change interrupt while GPIOEN=1, this interrupt can be used as PHY report the
link status change.
Indicates the received packet has filled the first data buffer.

CRC error or packet race tally counter overflow interrupt, software can maintain drivers
CRC error counter above 32 bit
PCI Bus error interrupt

Receive buffer unavailable

Transmit buffer underflow

Transmit error bit is set when a packet transmission is aborted due to excessive collisions.

This bit is set when a packet is received with one or more of the following errors:
1) CRC error, 2) Frame alignment error and 3) Missed packet.
This bit indicates that packet is transmitted with no errors.

This bit indicates that packet is received with no errors.

IMR

Interrupt Mask Register (0EH; Type=R/W )
All bits correspond to the bits in the ISR register. Power up=all 0s. Setting individual bits will
enable the corresponding interrupts.

EEPROM Configuration and status Register Group
EECSR EEPROM Command Status Register (74H, Type=R/W)

EEPROM programming status

EMBP

EEPROM embedded program enable, the VT86C100A will set this bit to zero after
programming complete.

LOAD

Dynamic reload EEPROM content, the PAR[5-0] will be update

DPM

Direct program EEPROM

ECS

EEPROM interface chip select status

ECK

EEPROM interface clock status

EDI

EEPROM interface data in status

EDO

EEPROM interface data out status

VIA Technologies, Inc.

Preliminary VT86C100A

MII port control and status Register Group
MIICR MII interface control register (070H, Type=R/W)

MII management port auto polling enable, MIICR has no effect while this set on

RCMD

read enable to read PHY status, reset while complete and PHY status will be store in
register MII data register 0x72

WCMD

write enable to program PHY, reset while PHY programmed completely

MDPM

direct program mode enable, while MDPM be set , the WCMD and RCMD have no effect

MOUT

MDIO output enable indicator while direct program mode

MDO

MII interface management port data output status

MDI

MII interface management port data input status

MDC

MII interface management port clock status

MIIAD MII CSR offset address register (071H, Type=R/W)

MSRCE

MDONE

MAD4

MII management port address bit 4

MAD3

MII management port address bit 3

MAD2

MII management port address bit 2

MAD1

MII management port address bit 1

MAD0

MII management port address bit 0

The MII management port address default value be (00001)b,

MIISR MII status register (06dH, Type=R/W)

GPIO1POL : General purpose I/O 1 pin output polarity, when this bit set as '1', the
GPIO1 pin output active high; set as '0', the GPIO1 pin output active low.

res

Reserve

MFDC

MFDC : Accelerate the MDC speed when VT86C100A enter MII auto polling; MFDC set
as '0', MDC be normal speed; or MFDC set as '1' , MDC be 4 times speed.

PHYOPT

PHYOPT : set 1 use default external PHY device address as 0001

MIIERR

MIIERR : PHY device coding error by insert RX_ERR, write to clear it.

MRERR

MRERR : MII Management read error, write to clear it

LNKFL

LNKFL : Link fail in 10 or 100MHz

SPEED

SPEED : Network speed, 0 as 100MHZ, 1 as 10MHz

PHYADR
MII configuration register (06cH, Type=R/W)

VIA Technologies, Inc.

Preliminary VT86C100A

VT5134A

VT3043E Bench Board

VIA TECHNOLOGIES, INC.

Thursday, September 04, 1997

Title

Size

Document Number

Rev

Date:

Sheet

EECS

MCRS
MCOL
MTXD3
MTXD2
MTXD1
MTXD0
MTXEN
MTXCK
MRXER
MRXCK
MRXDV
MRXD0
MRXD1
MRXD2
MRXD3
MDC
MDIO

M10TEN
PRTENL
PRTENH

TST
NC2
NC

HDRST

-BPRD

-PCIRST

MA[15:0]

MD[7:0]

-PME

|LINK
|2.SCH

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

39
41
43
45
47
49
51
53
55
57
59
61
63

65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101

103
105
107
109
111
113
115
117
119
121
123
125
127

40
42
44
46
48
50
52
54
56
58
60
62
64

66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

104
106
108
110
112
114
116
118
120
122
124
126
128

|3.SCH

PCIVCC

AD25

AD24

-CBE3

IDSEL

AD23
AD22

AD21

AD20
AD19

AD18

AD17

AD16
-CBE2

-FRAME

-IRDY

-TRDY

-DEVSEL

-STOP
-PERR

AD31

MCRS

PAR

-CBE1

AD30

MCOL

AD15

AD14

AD29

MTXD3

AD13

AD12

PCIVCC

AD28

MTXD2

AD11

AD10

-INTA

AD27

MTXD1

AD26

MTXD0

AD9

AD8

AD25

MTXEN

-CBE0

AD7

-PRSNT1

AD24

MTXCK

AD23

MRXER

-PRSNT2

AD22

MRDCK

AD21

MRXDV

AD20

MRXD0

AD6

AD5

AD19

MRXD1

AD4

-PCIRST

AD18

MRXD2

AD3

AD2

PCICLK

PCIVCC

AD17

MRXD3

AD1

AD0

-GNT

AD16

MDC

-REQ

AD15

MDIO

EECS

-BPRD

PCIVCC

-PME

AD14

MD0

MD1

AD31

AD30

AD13

M10TEN

MD2

MD3

AD29

AD12

PRTENL

MD4

AD28

AD11

PRTENH

MD5

AD27

AD26

AD10

MD6

MD7

AD25

AD9

MA15

PRTENL

PRTENH

AD24

AD8

MA14

MA0

MA1

-CBE3

IDSEL

AD7

MA13

AD23

AD6

MA12

AD22

AD5

MA11

AD21

AD20

AD4

MA10

AD19

AD3

MA9

AD18

AD2

MA8

MA2

MA3

AD17

AD16

AD1

MA7

MA4

MA5

-CBE2

AD0

MA6

MA7

-FRAME

MA5

MA8

SVDD

-IRDY

-CBE3

MA4

SVSS

-TRDY

-CBE2

MA3

MA9

-DEVSEL

-CBE1

MA2

MA10

MA11

-STOP

-CBE0

MA1

MA12

MA13

MA0

MA14

MA15

-PERR

IDSEL

NC2

-FRAME

MD7

-IRDY

MD6

TST

MCRS

PAR

-TRDY

MD5

MCOL

MTXD3

-CBE1

AD15

-DEVSEL

MD4

MTXD2

MTXD1

AD14

-STOP

MD3

MTXD0

MTXEN

AD13

PAR

MD2

AD12

AD11

PCICLK

MD1

MTXCK

MRXER

AD10

-INTA

MD0

MRXCK

MRXDV

AD9

-PCIRST
-GNT

EECS

-REQ

-BPRD

AD8

-CBE0

-PERR

AD7

-PME

TST

MRXD0

MRXD1

AD6

NC2

MRXD2

MRXD3

AD5

AD4

AD3

MDC

MDIO

AD2

HDRST

M10TEN

AD1

AD0

-INTA

-PCIRST

PCIVCC

PCICLK

SVDD

-GNT

-REQ

-PME

AD31

AD30

AD29

AD28

SVSS

AD27

AD26

MA[15:0]

MD[7:0]

.1u

JP1

HEADER 72X2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113

115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

2
4
6
8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

U1
VT3043E

AD30

122

AD29

123

AD28

124

AD27

127

AD26

128

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD0

CBE3

AD1

CBE2

CBE1

CBE0

IDSEL

FRAME

IRDY

TRDY

DEVSEL

STOP

PAR

PCICLK

115

INTA

113

PCIRST

114

GNT

118

REQ

119

PERR

AD31

121

VDD

SVDD

SVSS

PRTENH

PRTENL

MD7

MD6

MD5

MD4

MD3

MD2/EECK

MD1/EEDI

MD0/EEDO

MA15

MA14

MA13

MA12

MA11

MA10

MA9

MA8

MA7

MA6

MA5

MA4

MA3

MA2

MA1

MA0

MDIO

110

M10TEN

112

VSS

EECS

BPRD

VDD

VSS

MCRS

MCOL

MTXD3

MTXD2

MTXD1

MTXD0

MTXE

MTXC

MERR

100

MRXC

101

MRXDV

102

MRXD0

103

HDRST

111

MRXD2

105

MRXD1

104

MDC

109

MRXD3

106

PME

120

NC2

TST

VDD

VSS

107

VDD

108

VSS

116

VDD

117

VDD

125

VSS

126

R1
0

C8
.1u

C9
10uF

C10

.O1u

R2
3.6

0805

C11

.1u

C12

.1u

C13

.1u

C14

.1u

C15

.1u

PCI_CONA

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

PCI_CONB

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

CB1
22UF

CB2
22UF

CB3
22UF

CB4
22UF

CB5
22UF

CB8
22UF

CB7
22UF

VIA Technologies, Inc.

Preliminary VT86C100A

VT5134A

NS or Myson's PHY & Transceiver

VIA TECHNOLOGIES, INC.

Thursday, September 04, 1997

Title

Size

Document Number

Rev

Date:

Sheet

MTD972

NS 840

R22

R24

R23

V
V

OSC2

50M

25M

'*' for Myson PHY and Transceiver

R42

*Use RP1,RP2 or Only RP2 -> 510

SPEED10

TX_ER

TXO+/TXU+

MII_CRS

TXU-

TXO-

RXI+
RXI-

PUD01

MII_RXER

PTD+
PTD-

MDC

TXO+/TXU+

MDIO

PRD+

TXO-

PRD-

RESET

RXI+

PSD+

RXI-

REFIN

PSD-

CLK25
OSCIN

P3/100

AN0

SPEED10

AN1

RXI+

PUD02

RXI-

OSCIN

TXO+/TXU+

TXU-

P3/100

TXO-

PUD03

REFIN

CLK25

ANAVCC

FGND

TX_ER

RESET

PUD01

AN0

PUD03

PRD+
PRD-
PSD-

PUD01

PSD+

PTD-

AN1

PUD02

PTD+

ANAVCC

PUD03

MII_CRS

P3/100

MII_RXER

C16

.001u

R9
10K

DP83223

Transceiver

TXO+

TXO-

RXI+

RXI-

PMRD+

PMRD-

PMID+

PMID-

SD+

SD-

ENCSEL

LBEN

TXREF

TXVCC

RXVCC

TXGND

RXGND

EXTVCC

VCC

GND

EQSEL

/CDET

C17

10P

C18

.1u

C19

.1u

C20

.1u

C21

.1u

C22

.1u

C23

.1u

C24

.1u

C25

.1u

C26

.1u

C27

.1u

C28

.1u

C29

.1u

C30

.1u

C31

.1u

C32

.1u

C33

.1u

R10

4.7K

C34
.1u

R11

R12

R13

J1
RJ-45

1
2
3
4
5
6
7
8

PT4171

CT
TD+

TD-

RX+

RX-
TX+

TX-

RD+

2
3

R14

*2K

R15

R16

RN1
510

1
3
5
7

2
4
6
8

2N3904

R21

4.7K

R22
75

R23
0

R24

*75

OSC1

50MHz/*25MHz

VCC

OUT

GND

CX1

.1u

R25

510

R26
4.7K

R27
75

R28
75

R29

R30
75

C35
.1u

R31

R32
*0

R33
0

C37

.1u

C38

.1u

L2
47uH

C39
.1u

C40

22u

R35
0

R36

510

R37
*0

C41
*.1u

R38

47.5

R39
47.5

DP83840A

Physical Layer

TX_CLK

TXD3

TXD2

TXD1

TXD0

TX_EN

CRS_P2

COL

RXD3

RXD2

RXD1

RXD0

RX_CLK

RX_DV

RX_ER_P4

MDC

MDIO

TXU+

TXU-

TXS+

TXS-

RXI+

RXI-

TD+

TD-

RD+

RD-

SD+

SD-

SPEED_10

ENCSEL_P1

LBEN_P0

OSCIN

LED_TX

LED_RX

LED_LK

LED_P/F

LED_COL

REQ

RTX

CLK25M

REFIN

TX_ER

RX_EN

AN0

AN1

REPEATER

10BTSER

BPALIGN

BP4B5B

100

BPSCR

J_TD0

J_TDI

J_TRST

J_TCLK

J_TMS

RESET

PHYAD3

RES_0

VCC_A

PCSVCC_A

GND_A

PCSGND_A

VCC_B

REFVCC_B

GND_B

RCLKGND_B

GND_B

REFGND_B

RXVCC_C

TDVCC_C

PLLVCC_C

OVCC_C

RXGND_C

TDGND_C

PLLGND_C

OGND_C

ANAVCC_D

CRMVCC_D

ECLVCC_D

CGMVCC_D

OSCGND_D

ANAGND_D

CRMGND_D

CGMGND_D

C42
.1u

R40
*49.9

R41
*49.9

R42

*10K

R43

*4.7K

R44

*4.7K

R45

*4.7K

R46

*4.7K

R47

*4.7K

P/F

COL

100

R48
33

R49

R50
33

R51
33

RP1
82

2
3
4
5
6
7

RP2

130

2
3
4
5
6
7

R52

510

R53
510

R54
33
R55
33

R56
0

R57
*0

C43

*10p

U4A

74LS14

R58

10K

R59

10K

R60
10K

R61

10K

R62
10K

R63
4.7K

AN0

1
2
3

AN1

1
2
3

PHY0

1
2
3

PHY1

1
2
3

PHY2

1
2
3

PHY3

1
2
3

PHY4

1
2
3

R78
510

RN2
510

1
3
5
7

2
4
6
8

PWR

R17

10/0

R18
10/0

R20
39/49.9

R19

39/49.9

R81

R82

R79

0/75

R80

0/75

L4
FB

C47

39p

C48
39p

HDRST

-PCIRST

MTXCK

MTXD3
MTXD2
MTXD1
MTXD0

MTXEN

MCRS

MCOL

MRXD3
MRXD2
MRXD1
MRXD0

MRXCK
MRXDV
MRXER

MDIO

MDC

VIA Technologies, Inc.

Preliminary VT86C100A

VT5134A

VT3043E Strapping

VIA TECHNOLOGIES, INC.

Thursday, September 04, 1997

Title

Size

Document Number

Rev

Date:

Sheet

EECS

MD7

-BPRD

MD6
MD5
MD4
MD3
MD2
MD1
MD0

PCI_PWR

PCI_GOOD

ISOLATE

MD1

MD0

MD2

EECS

ALTRST

AUX_PWR

MA0

MD0

MA1

MD1

MA2

MD2

MA3

MD3

MA4

MD4

MA5

MD5

MA6

MD6

MA7

MD7

MA8
MA9
MA10
MA11
MA12
MA13

MA14
MA15

-BPRD

MD[7:0]

MA[15:0]

1
3

10
12

14
16

1
2
3
4
5
6
7
8

RP3

10K

2
3
4
5
6
7
8
9

RP4

10K

2
3
4
5
6
7
8
9

1
3

10
12

14
16

1
2
3
4
5
6
7
8

RP5

4.7K

2
3
4
5
6
7
8
9

RP6

4.7K

2
3
4
5
6
7
8
9

93C46

VCC

GND

27512

A10

A11

A12

A13

A14

A15

R64
0

R65
0

R66
4.7K

R67

4.7K

TL7705A

REF

RESIN

GND

VCC

SENSE

RESET

Q4
NPN

1N4148

TP1

TP2

TP3

TP4

TP5

R68

R69

R70

R71

10K

R72

7.8K

R73

10K

R74

10K

R75

100K

C44

100p

R76
4.7K

R77
0

C45

.1u

C46

.1u

AUX5V_CON

AUX5V

GND

WAKUP

GND

AUX5V

U8A

74HC14

U8B

74HC14

U8C

74HC14

U8D

74HC14

MD[7:0]

EECS

-BPRD

M10TEN

PRTENH

PRTENL

TST

NC2

MA[15:0]

-PME

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: VT86C100A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: VT86C100A