Si3831DV
Vishay Siliconix
Document Number: 70785
S-56947--Rev. C, 28-Dec-98
www.vishay.com
S
FaxBack 408-970-5600
2-1
Bi-Directional P-Channel MOSFET/Power Switch
PRODUCT SUMMARY
V
DS
(V)
r
DS(on)
(
W
)
I
D
(A)
"
7
0.170 @ V
GS
= 4.5 V
"
2.4
"
7
0.240 @ V
GS
= 2.5 V
"
2.0
FEATURES
D
Low r
DS(on)
Symmetrical P-Channel MOSFET
D
Integrated Body Bias For Bi-Directional Blocking
D
2.5- to 5.5-V Operation
D
Exceeds
"
2 kV ESD Protected
D
Solution for High-Side Battery Disconnect Switching (BDS)
D
Supports Battery Switching in Multiple Battery Cell
Phones, PDAs and PCS Products
D
Low Profile, Small Footprint TSOP-6 Package
DESCRIPTION
The Si3831DV is a low on-resistance p-channel power
MOSFET providing bi-directional blocking and conduction.
Bi-directional blocking is facilitated by combining a 4-terminal
symmetric p-channel MOSFET with a body bias selector
circuit*. Circuit operation automatically biases the p-channel
body to the most positive source/drain potential thereby
maintaining a reverse bias across the diode present between
the source/drain terminals. Off-state device blocking
characteristics are symmetric, facilitating bi-directional
blocking for high-side battery switching in portable products.
Gate drive is facilitated by negatively biasing the gate relative
to the body potential. The off-state is achieved by biasing the
gate to the most positive supply voltage or to the body
potential. The Si3831DV is available in a 6-pin TSOP-6
package rated for the 25 to 85
C commercial temperature
range.
APPLICATION CIRCUITS
FIGURE 1. Charger Demultiplexing
Loads
Charger
AC/DC
Adapter
Body
Bias
Body
Bias
FIGURE 2. Battery Multiplexing (High-Side Switch)
Body
Bias
Charger
DC/DC
Body
Bias
Si3831DV
Si3831DV
Si3831DV
Si3831DV
*Patents pending.
Si3831DV
Vishay Siliconix
www.vishay.com
S
FaxBack 408-970-5600
2-2
Document Number: 70785
S-56947--Rev. C, 28-Dec-98
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
S/D
(6)
G
(3)
D/S
(4)
P-Channel MOSFET
BODY
(1)
Body
Bias
Generator
SUBSTRATE (GND)
(2, 5)
ESD
Protection
TSOP-6
Top View
6
4
1
2
3
5
2.75 mm
3 mm
BODY
SUB
G
S/D
SUB
D/S
FIGURE 3.
FIGURE 4.
ABSOLUTE MAXIMUM RATINGS (T
A
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage, Source-Drain Voltage
a
V
DS
7.0 to +7.0
V
Source-Body/Drain-Body/Gate-Body Voltage
V
SB
, V
DB
, V
GB
0.3 to 7.0
V
Body-Substrate Voltage
V
BSUB
+7.0 to 0.3
Continuous Drain-to-Source Current
(T
J
= 150
_
C)
a, b
T
A
= 25
_
C
I
D
"
2.4
A
Continuous Drain-to-Source Current
(T
J
= 150
_
C)
a, b
T
A
= 70
_
C
I
D
"
2.0
A
Pulsed Drain-to-Source Current
a
I
DM
"
8
Maximum Power Dissipation
b
T
A
= 25
_
C
P
D
1.5
W
Maximum Power Dissipation
b
T
A
= 70
_
C
P
D
1.0
W
Operating Junction and Storage Temperature Range
T
J
, T
stg
55 to 150
_
C
RECOMMENDED OPERATING RANGE
Parameter
Symbol
Range
Unit
Drain-Source Voltage
a
V
DS
, V
DS
5.5 to 5.5
V
Gate-Drain,/Gate-Source Voltage
V
GD
, V
GS
0 to 5.5
V
Source-Body/Drain-Body/Gate-Body Voltage
V
SB
, V
DB
, V
GB
0 to 5.5
Drain-to-Source Current
a, b
I
DS
"
2.4
A
Body-Source Current
I
BS
0 to 10
m
A
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Limit
Unit
Maximum Junction-to-Ambient
b
R
thJA
80
_
C/W
Maximum Junction-to-Ambient
b
R
thJA
125
C/W
Notes
a.
Bi-directional.
b.
Surface Mounted on FR4 Board, t
v
5 sec.
c.
Surface Mounted on FR4 Board, SteadyState.
Si3831DV
Vishay Siliconix
Document Number: 70785
S-56947--Rev. C, 28-Dec-98
www.vishay.com
S
FaxBack 408-970-5600
2-3
SPECIFICATIONS (V
BS
= 0 V, T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
m
A
0.4
V
Gate-Body Leakage
I
GSS
V
DS
= 0 V, V
GS
= 5.5 V to +0.3 V
"
100
nA
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 5.5 V, V
GS
= 0 V, V
SB
= 0 V
1
m
A
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 5.5 V, V
GS
= 0 V, V
SB
= 0 V, T
J
= 70
_
C
5
m
A
On-State Drain Current
a
I
D(on)
V
DS
= 3 V, V
GS
= 4.5 V
8
A
On-State Drain Current
a
I
D(on)
V
DS
= 3 V, V
GS
= 2.5 V
3
A
Drain Source On State Resistance
a
r
DS(
)
V
GS
= 4.5 V, I
D
= 2.4 A
0.130
0.170
W
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= 2.5 V, I
D
= 2.0
A
0.180
0.240
W
Dynamic
b
Total Gate Charge
Q
g
V
5 V V
4 5 V I
2 4 A
2.0
4.0
C
Gate-Source Charge
Q
gs
V
DS
= 5 V,
V
GS
= 4.5 V, I
D
= 2.4 A
0.23
nC
Gate-Drain Charge
Q
gd
0.14
Turn-On Delay Time
t
d(on)
V
3 V R
3
W
12
25
Rise Time
t
r
V
DD
= 3 V, R
L
= 3
W
I
1 0 A V
4 5 V R
6
W
55
110
ns
Turn-Off Delay Time
t
d(off)
DD
,
L
I
D
^
1.0 A, V
GEN
= 4.5 V, R
G
= 6
W
90
180
ns
Fall Time
t
f
85
170
Notes
a.
Pulse test; pulse width
v
300
m
s, duty cycle
v
2%.
b.
Guaranteed by design, not subject to production testing.
GATE BUFFER REFERENCE
FIGURE 5. Gate Buffer Referenced to Most Positive Supply
Body
Bias
Load
IN
FIGURE 6. Gate Buffer Referenced to Body Bias Pin
Load
IN
Body
Bias
Si3831DV
Si3831DV
Si3831DV
Vishay Siliconix
www.vishay.com
S
FaxBack 408-970-5600
2-4
Document Number: 70785
S-56947--Rev. C, 28-Dec-98
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
0
2
4
6
8
0
1
2
3
4
5
0
0.9
1.8
2.7
3.6
4.5
0
0.4
0.8
1.2
1.6
2.0
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
50
25
0
25
50
75
100
125
150
0
0.1
0.2
0.3
0.4
0
2
4
6
8
0
50
100
150
200
250
0
1
2
3
4
5
6
0
2
4
6
8
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Characteristics
Transfer Characteristics
Gate Charge
On-Resistance vs. Drain Current
V
DS
Drain-to-Source Voltage (V)
Drain Current (A)
I
D
V
GS
Gate-to-Source Voltage (V)
Drain Current (A)
I
D
Gate-to-Source V
oltage
(V)
Q
g
Total Gate Charge (nC)
V
DS
Drain-to-Source Voltage (V)
C Capacitance (pF)
V
GS
On-Resistance (
r
DS(on)
W
)
I
D
Drain Current (A)
Capacitance
On-Resistance vs. Junction Temperature
V
GS
= 4.5 V
I
D
= 2.4 A
T
J
Junction Temperature (
_
C)
(Normalized)
On-Resistance (
r
DS(on)
W
)
V
GS
= 5 thru 3 V
1.5 V
2 V
2.5 V
1 V
T
C
= 55
_
C
125
_
C
25
_
C
V
GS
= 4.5 V
V
GS
= 2.5 V
C
rss
C
oss
C
iss
V
DS
= 3 V
I
D
= 2.4 A
Si3831DV
Vishay Siliconix
Document Number: 70785
S-56947--Rev. C, 28-Dec-98
www.vishay.com
S
FaxBack 408-970-5600
2-5
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
0
3
6
9
12
15
0.01
0.10
1.00
10.00
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Threshold Voltage
Single Pulse Power
Normalized Thermal Transient Impedance, Junction-to-Ambient
Square Wave Pulse Duration (sec)
Normalized Ef
fective
T
ransient
Thermal Impedance
On-Resistance (
r
DS(on)
W
)
V
SD
Source-to-Drain Voltage (V)
V
GS
Gate-to-Source Voltage (V)
Source Current (A)
I
S
T
J
Temperature (
_
C)
Time (sec)
Power (W)
0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
5
6
0.2
0.1
0.0
0.1
0.2
0.3
0.4
50
25
0
25
50
75
100
125
150
T
J
= 150
_
C
T
J
= 25
_
C
I
D
= 2.4 A
I
D
= 250
m
A
V
ariance (V)
V
GS(th)
8
1
0.1
2
1
0.1
0.01
10
4
10
3
10
2
10
1
1
10
30
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 80
_
C/W
3. T
JM
T
A
= P
DM
Z
thJA
(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
I
D
= 0.5 A
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